clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSI

Add SSI clocks, resets and power domains support for the SSI blocks
available on the Renesas RZ/G3S SoC.

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241113133540.2005850-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index b2ae8cdc4723e6d8328d7f18cf27c0534e21061e..573d856ffe0671086f4e505dd4d8ecdec5623baa 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -209,6 +209,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
        DEF_MOD("sdhi2_imclk2",         R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
        DEF_MOD("sdhi2_clk_hs",         R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
        DEF_MOD("sdhi2_aclk",           R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
+       DEF_MOD("ssi0_pclk2",           R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0),
+       DEF_MOD("ssi0_sfr",             R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1),
+       DEF_MOD("ssi1_pclk2",           R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2),
+       DEF_MOD("ssi1_sfr",             R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3),
+       DEF_MOD("ssi2_pclk2",           R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4),
+       DEF_MOD("ssi2_sfr",             R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5),
+       DEF_MOD("ssi3_pclk2",           R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6),
+       DEF_MOD("ssi3_sfr",             R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7),
        DEF_MOD("usb0_host",            R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0),
        DEF_MOD("usb1_host",            R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1),
        DEF_MOD("usb0_func",            R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2),
@@ -238,6 +246,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
        DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
        DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
        DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
+       DEF_RST(R9A08G045_SSI0_RST_M2_REG, 0x870, 0),
+       DEF_RST(R9A08G045_SSI1_RST_M2_REG, 0x870, 1),
+       DEF_RST(R9A08G045_SSI2_RST_M2_REG, 0x870, 2),
+       DEF_RST(R9A08G045_SSI3_RST_M2_REG, 0x870, 3),
        DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0),
        DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1),
        DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2),
@@ -286,6 +298,14 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
                                DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0),
        DEF_PD("sdhi2",         R9A08G045_PD_SDHI2,
                                DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0),
+       DEF_PD("ssi0",          R9A08G045_PD_SSI0,
+                               DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0),
+       DEF_PD("ssi1",          R9A08G045_PD_SSI1,
+                               DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0),
+       DEF_PD("ssi2",          R9A08G045_PD_SSI2,
+                               DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0),
+       DEF_PD("ssi3",          R9A08G045_PD_SSI3,
+                               DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0),
        DEF_PD("usb0",          R9A08G045_PD_USB0,
                                DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0),
        DEF_PD("usb1",          R9A08G045_PD_USB1,