mips: dts: cameo-rtl9302c: Add switch block

Add the switch port and phys to the cameo-rtl9302c-2x-rtl8224-2xge
board.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts
index 6789bf3740446ea30edab781d12a19fdaee21d33..6f6a05d4088e18d7cd67fd6b85873cb6e95d03be 100644 (file)
--- a/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts
+++ b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts
@@ -71,3 +71,99 @@
                };
        };
 };
+
+&mdio0 {
+       /* External RTL8224 */
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+       };
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+       };
+       phy2: ethernet-phy@2 {
+               reg = <2>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+       };
+       phy3: ethernet-phy@3 {
+               reg = <3>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+       };
+};
+
+&mdio1 {
+       /* External RTL8224 */
+       phy4: ethernet-phy@0 {
+               reg = <0>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+       };
+       phy5: ethernet-phy@1 {
+               reg = <1>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+       };
+       phy6: ethernet-phy@2 {
+               reg = <2>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+       };
+       phy7: ethernet-phy@3 {
+               reg = <3>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+       };
+};
+
+&switch0 {
+       ethernet-ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+                       phy-handle = <&phy0>;
+                       phy-mode = "usxgmii";
+               };
+               port@1 {
+                       reg = <1>;
+                       phy-handle = <&phy1>;
+                       phy-mode = "usxgmii";
+               };
+               port@2 {
+                       reg = <2>;
+                       phy-handle = <&phy2>;
+                       phy-mode = "usxgmii";
+               };
+               port@3 {
+                       reg = <3>;
+                       phy-handle = <&phy3>;
+                       phy-mode = "usxgmii";
+               };
+               port@16 {
+                       reg = <16>;
+                       phy-handle = <&phy4>;
+                       phy-mode = "usxgmii";
+               };
+               port@17 {
+                       reg = <17>;
+                       phy-handle = <&phy5>;
+                       phy-mode = "usxgmii";
+               };
+               port@18 {
+                       reg = <18>;
+                       phy-handle = <&phy6>;
+                       phy-mode = "usxgmii";
+               };
+               port@19 {
+                       reg = <19>;
+                       phy-handle = <&phy7>;
+                       phy-mode = "usxgmii";
+               };
+               port@24{
+                       reg = <24>;
+                       phy-mode = "10gbase-r";
+               };
+               port@25{
+                       reg = <25>;
+                       phy-mode = "10gbase-r";
+               };
+       };
+};