]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
wifi: rtw89: 8852c: Fix rtw8852c_pwr_{on,off}_func() for USB
authorBitterblue Smith <rtl8821cerfe2@gmail.com>
Sat, 1 Nov 2025 19:24:39 +0000 (21:24 +0200)
committerPing-Ke Shih <pkshih@realtek.com>
Tue, 4 Nov 2025 01:34:53 +0000 (09:34 +0800)
There are a few differences in the power on/off functions between PCIE
and USB. The changes in the power off function in particular are needed
for the RTL8832CU to be able to power on again after it's powered off.

While the RTL8832CU appears to work without the changes in the power on
function, it's probably best to implement them, in case they are needed
in some situations.

Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
Acked-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/598dec66-b5cc-435a-bcf6-fa66577f8cfc@gmail.com
drivers/net/wireless/realtek/rtw89/rtw8852c.c

index ee191530737676a203663ab5818db29e75de02eb..6aedbd03e3d49c079b8b604770ad216624f69a52 100644 (file)
@@ -214,7 +214,8 @@ static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
        int ret;
 
        val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK);
-       if (val32 == MAC_AX_HCI_SEL_PCIE_USB)
+       if (val32 == MAC_AX_HCI_SEL_PCIE_USB ||
+           rtwdev->hci.type == RTW89_HCI_TYPE_USB)
                rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L);
 
        rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
@@ -246,7 +247,9 @@ static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
        rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
 
        rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
-       rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
+
+       if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
+               rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
 
        rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN);
        rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP);
@@ -305,9 +308,11 @@ static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
 
        rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
        rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
-       rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
-                         B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN |
-                         B_AX_LED1_PULL_LOW_EN);
+
+       if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
+               rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
+                                 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN |
+                                 B_AX_LED1_PULL_LOW_EN);
 
        rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
                          B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
@@ -385,12 +390,24 @@ static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
        if (ret)
                return ret;
 
-       rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
+       if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
+               rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
+       else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
+               rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_EDSWR);
+
        rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
        rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
        rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
                           B_AX_REG_ZCDC_H_MASK, 0x3);
-       rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
+
+       if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
+               rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
+       } else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) {
+               val32 = rtw89_read32(rtwdev, R_AX_SYS_PW_CTRL);
+               val32 &= ~B_AX_AFSM_PCIE_SUS_EN;
+               val32 |= B_AX_AFSM_WLSUS_EN;
+               rtw89_write32(rtwdev, R_AX_SYS_PW_CTRL, val32);
+       }
 
        return 0;
 }