This commit was manufactured by cvs2svn to create branch

'gcc-3_3-branch'.

From-SVN: r74679

diff --git a/gcc/testsuite/gcc.c-torture/execute/20031215-1.c b/gcc/testsuite/gcc.c-torture/execute/20031215-1.c
new file mode 100644 (file)
index 0000000..d62177b
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/20031215-1.c
@@ -0,0 +1,38 @@
+/* PR middle-end/13400 */
+/* The following test used to fail at run-time with a write to read-only
+   memory, caused by if-conversion converting a conditional write into an
+   unconditional write.  */
+
+typedef struct {int c, l; char ch[3];} pstr;
+const pstr ao = {2, 2, "OK"};
+const pstr * const a = &ao;
+
+void test1(void)
+{
+    if (a->ch[a->l]) {
+        ((char *)a->ch)[a->l] = 0;
+    }
+}
+
+void test2(void)
+{
+    if (a->ch[a->l]) {
+        ((char *)a->ch)[a->l] = -1;
+    }
+}
+
+void test3(void)
+{
+    if (a->ch[a->l]) {
+        ((char *)a->ch)[a->l] = 1;
+    }
+}
+
+int main(void)
+{
+    test1();
+    test2();
+    test3();
+    return 0;
+}
+

diff --git a/gcc/testsuite/gcc.dg/altivec-10.c b/gcc/testsuite/gcc.dg/altivec-10.c
new file mode 100644 (file)
index 0000000..8d9223f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/altivec-10.c
@@ -0,0 +1,86 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */
+
+#include <altivec.h>
+#include <signal.h>
+
+void 
+sig_ill_handler (int sig)
+{
+    exit(0);
+}
+
+typedef union
+{
+  float         f[4];
+  unsigned int  i[4];
+  vector float  v;
+} vec_float_t;
+
+void 
+check_vec_all_num ()
+{
+  vec_float_t a, b, c;
+
+  a.i[0] = 0xfffa5a5a;
+  a.f[1] = 1.0;
+  a.f[2] = 1.0;
+  a.f[3] = 1.0;
+
+  b.f[0] = 1.0;
+  b.f[1] = 1.0;
+  b.f[2] = 1.0;
+  b.f[3] = 1.0;
+
+  c.i[0] = 0xfffa5a5a;
+  c.i[1] = 0xfffa5a5a;
+  c.i[2] = 0xfffa5a5a;
+  c.i[3] = 0xfffa5a5a;
+
+  if (vec_all_numeric (a.v))
+    abort ();
+
+  if (vec_all_nan (a.v))
+    abort ();
+
+  if (!vec_all_numeric (b.v))
+    abort ();
+
+  if (vec_all_nan (b.v))
+    abort ();
+
+  if (vec_all_numeric (c.v))
+    abort ();
+
+  if (!vec_all_nan (c.v))
+    abort ();
+
+}
+
+void 
+check_cmple()
+{
+  vector float a = {1.0, 2.0, 3.0, 4.0};
+  vector float b = {1.0, 3.0, 2.0, 5.0};
+  vector signed int aux;
+  vector signed int le = {-1, -1, 0, -1};
+
+  aux = vec_cmple (a, b);
+
+  if (!vec_all_eq (aux, le))
+    abort ();
+}
+
+
+int 
+main()
+{
+  /* Exit on systems without altivec.  */
+  signal (SIGILL, sig_ill_handler);
+  asm volatile ("vor 0,0,0");
+  signal (SIGILL, SIG_DFL);
+
+  check_cmple ();
+  check_vec_all_num ();
+  exit (0);
+}