]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
[PATCH] RISC-V: Minimal support for zama16b extension.
authorDongyan Chen <chendongyan@isrc.iscas.ac.cn>
Wed, 7 May 2025 17:33:06 +0000 (11:33 -0600)
committerJeff Law <jlaw@ventanamicro.com>
Wed, 7 May 2025 17:33:41 +0000 (11:33 -0600)
This patch support zama16b extension[1].
To enable GCC to recognize and process zama16b extension correctly at compile time.

[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv.opt: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-48.c: New test.

gcc/common/config/riscv/riscv-common.cc
gcc/config/riscv/riscv.opt
gcc/testsuite/gcc.target/riscv/arch-48.c [new file with mode: 0644]

index 0233e1a108be8a41a5533ba4ea8738f558669984..ca14eb96b2533e12f03d872ca4b50c521a3d9a30 100644 (file)
@@ -327,6 +327,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zabha", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zacas", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zama16b", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1657,6 +1658,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   RISCV_EXT_FLAG_ENTRY ("zalrsc",  x_riscv_za_subext, MASK_ZALRSC),
   RISCV_EXT_FLAG_ENTRY ("zabha",   x_riscv_za_subext, MASK_ZABHA),
   RISCV_EXT_FLAG_ENTRY ("zacas",   x_riscv_za_subext, MASK_ZACAS),
+  RISCV_EXT_FLAG_ENTRY ("zama16b", x_riscv_za_subext, MASK_ZAMA16B),
 
   RISCV_EXT_FLAG_ENTRY ("zba", x_riscv_zb_subext, MASK_ZBA),
   RISCV_EXT_FLAG_ENTRY ("zbb", x_riscv_zb_subext, MASK_ZBB),
index 9e471be4055c68c58e860843eafbf137b80f098a..80593ee139c10fca9c9904ef50ed1b52658bb324 100644 (file)
@@ -274,6 +274,8 @@ Mask(ZA64RS)  Var(riscv_za_subext)
 
 Mask(ZA128RS) Var(riscv_za_subext)
 
+Mask(ZAMA16B) Var(riscv_za_subext)
+
 TargetVariable
 int riscv_zb_subext
 
diff --git a/gcc/testsuite/gcc.target/riscv/arch-48.c b/gcc/testsuite/gcc.target/riscv/arch-48.c
new file mode 100644 (file)
index 0000000..58a558e
--- /dev/null
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zama16b -mabi=lp64" } */
+int foo()
+{
+}