arm64: dts: qcom: monaco: Complete SDHC definition

Add the missing SDHC properties required to enable HS200, HS400,
and HS400 Enhanced Strobe modes, as supported by this controller.

Select the proper default pinctrls.

Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260116214354.256878-2-loic.poulain@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 5d2df4305d1c1c450c7be53614da9d8c08123e66..12333709206c28e8786905c7daf58c5378721097 100644 (file)
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -4740,11 +4740,21 @@
                        interconnect-names = "sdhc-ddr",
                                             "cpu-sdhc";
 
+                       pinctrl-names = "default", "sleep";
+                       pinctrl-0 = <&sdc1_state_on>;
+                       pinctrl-1 = <&sdc1_state_off>;
+
                        qcom,dll-config = <0x000f64ee>;
                        qcom,ddr-config = <0x80040868>;
+                       bus-width = <8>;
                        supports-cqe;
                        dma-coherent;
 
+                       mmc-ddr-1_8v;
+                       mmc-hs200-1_8v;
+                       mmc-hs400-1_8v;
+                       mmc-hs400-enhanced-strobe;
+
                        status = "disabled";
 
                        sdhc1_opp_table: opp-table {