enum PP_OD_DPM_TABLE_COMMAND type,
long input[], uint32_t size);
-void smu_v15_0_set_smu_mailbox_registers(struct smu_context *smu);
-
int smu_v15_0_enable_thermal_alert(struct smu_context *smu);
int smu_v15_0_disable_thermal_alert(struct smu_context *smu);
.get_dpm_clock_table = smu_v15_0_common_get_dpm_table,
};
-static void smu_v15_0_0_set_smu_mailbox_registers(struct smu_context *smu)
-{
- struct amdgpu_device *adev = smu->adev;
-
- smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_32);
- smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_30);
- smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_31);
-}
-
static void smu_v15_0_0_init_msg_ctl(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
void smu_v15_0_0_set_ppt_funcs(struct smu_context *smu)
{
-
smu->ppt_funcs = &smu_v15_0_0_ppt_funcs;
- smu->message_map = smu_v15_0_0_message_map;
smu->feature_map = smu_v15_0_0_feature_mask_map;
smu->table_map = smu_v15_0_0_table_map;
smu->is_apu = true;
- smu_v15_0_0_set_smu_mailbox_registers(smu);
smu_v15_0_0_init_msg_ctl(smu);
}