rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932]

As PR109932 shows, builtins __builtin_{un,}pack_vector_int128
should be guarded under vsx rather than power7, as their
corresponding bif patterns have the conditions TARGET_VSX
and VECTOR_MEM_ALTIVEC_OR_VSX_P (V1TImode).  This patch is to
ensure __builtin_{un,}pack_vector_int128 only available under
vsx.

	PR target/109932

gcc/ChangeLog:

	* config/rs6000/rs6000-builtin.def (BU_VSX_MISC_2): New macro.
	({un,}pack_vector_int128): Use BU_VSX_MISC_2 instead of
	BU_P7_MISC_2.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/pr109932-1.c: New test.
	* gcc.target/powerpc/pr109932-2.c: New test.

(cherry picked from commit db291447877aae67979ce3655fcc6fc877f57c6a)

diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 36ba145ad3d23e774c317532c278a2d5cfcac4bb..52ca2416e36a712b33739306814103f1e2eb6929 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -320,6 +320,14 @@
                     | RS6000_BTC_SPECIAL),                             \
                    CODE_FOR_nothing)                   /* ICODE */
 
+#define BU_VSX_MISC_2(ENUM, NAME, ATTR, ICODE)                         \
+  RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM,             /* ENUM */      \
+                   "__builtin_" NAME,                  /* NAME */      \
+                   RS6000_BTM_VSX,                     /* MASK */      \
+                   (RS6000_BTC_ ## ATTR                /* ATTR */      \
+                    | RS6000_BTC_BINARY),                              \
+                   CODE_FOR_ ## ICODE)                 /* ICODE */
+
 /* VSX overloaded builtin function macros.  */
 #define BU_VSX_OVERLOAD_1(ENUM, NAME)                                  \
   RS6000_BUILTIN_1 (VSX_BUILTIN_VEC_ ## ENUM,          /* ENUM */      \
@@ -2589,8 +2597,8 @@ BU_LDBL128_2 (UNPACK_TF,  "unpack_longdouble",    CONST,  unpacktf)
 BU_IBM128_2 (PACK_IF,          "pack_ibm128",          CONST,  packif)
 BU_IBM128_2 (UNPACK_IF,                "unpack_ibm128",        CONST,  unpackif)
 
-BU_P7_MISC_2 (PACK_V1TI,       "pack_vector_int128",   CONST,  packv1ti)
-BU_P7_MISC_2 (UNPACK_V1TI,     "unpack_vector_int128", CONST,  unpackv1ti)
+BU_VSX_MISC_2 (PACK_V1TI,      "pack_vector_int128",   CONST,  packv1ti)
+BU_VSX_MISC_2 (UNPACK_V1TI,    "unpack_vector_int128", CONST,  unpackv1ti)
 
 /* 2 argument DFP (Decimal Floating Point) functions added in ISA 3.0.  */
 BU_P9_DFP_MISC_2 (TSTSFI_LT_DD, "dtstsfi_lt_dd", CONST, dfptstsfi_lt_dd)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
new file mode 100644 (file)
index 0000000..374d9f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
@@ -0,0 +1,17 @@
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* Verify there is no ICE but one expected error message instead.  */
+
+#include <altivec.h>
+
+extern vector signed __int128 res_vslll;
+extern unsigned long long aull[2];
+
+void
+testVectorInt128Pack ()
+{
+  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
+}
+

diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
new file mode 100644 (file)
index 0000000..374d9f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
@@ -0,0 +1,17 @@
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* Verify there is no ICE but one expected error message instead.  */
+
+#include <altivec.h>
+
+extern vector signed __int128 res_vslll;
+extern unsigned long long aull[2];
+
+void
+testVectorInt128Pack ()
+{
+  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
+}
+