arm64: dts: rockchip: Move dsi address+size-cells from SoC to px30 boards

The #address-cells and #size-cells properties are not useful on the DSI
controller node; they are only useful/required on ports and panel(s).
So remove them from the controller node and add them where actually
needed on the various px30 based boards, which includes rk3326.

This fixes the following DTB validation warnings:

  unnecessary #address-cells/#size-cells without "ranges",
  "dma-ranges" or child "reg" property

Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
Link: https://lore.kernel.org/r/20250709132323.128757-2-didi.debian@cknow.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts
index 1d26164be7b86126c2cdf8b9cdcc8057a523eb2d..a31c61c8f148dcbdd7c67a091b86200e1337764a 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w-a2.dts
@@ -12,6 +12,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        panel@0 {

diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts
index 82c6acdb4fae7ad7f88794191fcdb2946dae8733..a3c6edfdb37cd5aaf5951ee8f64785af45d9ff89 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3146w.dts
@@ -12,6 +12,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        panel@0 {

diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts
index 94449132df387b7ee964ce49307c020f57b5e558..9b5eff392dfa10a07a827df59be7736718d61c4e 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk050h3148w.dts
@@ -12,6 +12,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        panel@0 {

diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts
index d7b639e7ccab0825b039834d8dc1375af12ea0ed..36b7cae49e31306c483aecf101e68880431c1273 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-cobra-ltk500hd1829.dts
@@ -16,6 +16,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        panel@0 {

diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index bfd724b73c9a7647f661b4799df00edd838f1085..85d1642eb9bee03cb7a532be0e1fd3ac80d61666 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -124,6 +124,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        ports {

diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts
index b71929bcb33e6a7d792246cda2feccc4fa370ed5..932721ffd47075ec67749b3cc071559f59f7d417 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3146w-a2.dts
@@ -12,6 +12,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        panel@0 {

diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts
index a9bd5936c701ac2e5080bee14c27b03056c764c5..70adf091371c3307b40daabfb22330528e8ae71d 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-pp1516-ltk050h3148w.dts
@@ -12,6 +12,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        panel@0 {

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 0cad83c5d5fe64dc8539e0fd0640e02058e1955c..5034ad8019a8f9fcbff2c73dfdf33829a7a57cf5 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -1137,8 +1137,6 @@
                resets = <&cru SRST_MIPIDSI_HOST_P>;
                reset-names = "apb";
                rockchip,grf = <&grf>;
-               #address-cells = <1>;
-               #size-cells = <0>;
                status = "disabled";
 
                ports {

diff --git a/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi
index 150fadcb0b3c395fc1ea33e1696f3c1f60fb8b69..54395a40b087a546aa35bdc29eefee53a85ccfaf 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi
@@ -118,6 +118,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        ports {

diff --git a/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts b/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts
index 10e6ab724ac4510fea6b2019dc96b3a56b10605e..4d306085646c1200ebb81d93636e9bd6636ffce4 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts
@@ -322,6 +322,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        internal_display: panel@0 {

diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
index 446a1a6c12e7eb52d7505cc1db655982769db4f3..bf4554eff47d34bd167d6f7c0e97a77b311111b7 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
@@ -220,6 +220,8 @@
 };
 
 &dsi {
+       #address-cells = <1>;
+       #size-cells = <0>;
        status = "okay";
 
        ports {