- const: sw3
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
description: phandle pointing to the mmio-sram device node
required:
maxItems: 64
sram:
- $ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
- items:
- maxItems: 1
- description: |
- phandles to one or more reserved on-chip SRAM regions.
+ description:
phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
a4xx Snapdragon SoCs. See
Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
maxItems: 1
sram:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- description: A phandle array with inner size 1 (no arg cells).
- First phandle is the LCPA (Logical Channel Parameter Address) memory.
- Second phandle is the LCLA (Logical Channel Link base Address) memory.
- maxItems: 2
items:
- maxItems: 1
+ - description: LCPA (Logical Channel Parameter Address) memory.
+ - description: LCLA (Logical Channel Link base Address) memory.
memcpy-channels:
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 1
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
description:
The VPU uses the SRAM to store some of the reference data instead of
storing it on DMA memory. It is mainly used for the purpose of reducing
maxItems: 5 # Wrapper and 4 slots
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
description:
- Optional phandle to a reserved on-chip SRAM regions. The SRAM can
- be used for descriptor storage, which may improve bus utilization.
+ The SRAM can be used for descriptor storage, which may improve bus
+ utilization.
required:
- compatible
maxItems: 1
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
- phandle to a reserved on-chip SRAM regions.
+ maxItems: 1
+ description:
Some SoCs, like rk3588 provide on-chip SRAM to store temporary
buffers during decoding.
maxItems: 1
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
description:
- phandle to a reserved SRAM region which is used as temporary
- storage memory between DMA and MDMA engines.
+ SRAM region which is used as temporary storage memory between DMA and
+ MDMA engines.
port:
$ref: /schemas/graph.yaml#/$defs/port-base
- const: ppe
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: phandle to mmio SRAM
+ maxItems: 1
mediatek,ethsys:
$ref: /schemas/types.yaml#/definitions/phandle
- ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
description:
phandle to MSMC SRAM node
- ti,am3359-prueth # for AM33x SoC family
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
description:
phandle to OCMC SRAM node
minItems: 1
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
- phandles to a reserved SRAM region which is used as the memory of
- the ARC core. The region should be defined as child nodes of the
- AHB SRAM node as per the generic bindings in
- Documentation/devicetree/bindings/sram/sram.yaml
+ maxItems: 1
amlogic,secbus2:
$ref: /schemas/types.yaml#/definitions/phandle
# --------------------
sram:
- $ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
- items:
- maxItems: 1
- description: |
- phandles to one or more reserved on-chip SRAM regions. The regions
- should be defined as child nodes of the respective SRAM node, and
- should be defined as per the generic bindings in,
- Documentation/devicetree/bindings/sram/sram.yaml
allOf:
- if:
at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
sram:
- $ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
- items:
- maxItems: 1
- description: |
- phandles to one or more reserved on-chip SRAM regions. The regions
- should be defined as child nodes of the respective SRAM node, and
- should be defined as per the generic bindings in,
- Documentation/devicetree/bindings/sram/sram.yaml
required:
- compatible
- const: rx
sram:
- $ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 8
- items:
- maxItems: 1
- description: |
+ description:
phandles to one or more reserved on-chip SRAM regions. Other than TCM,
the RPU can execute instructions and access data from the OCM memory,
the main DDR memory, and other system memories.
- The regions should be defined as child nodes of the respective SRAM
- node, and should be defined as per the generic bindings in
- Documentation/devicetree/bindings/sram/sram.yaml
-
memory-region:
description: |
List of phandles to the reserved memory regions associated with the
- const: rxm2m
sram:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: |
- Phandles to a reserved SRAM region which is used as temporary
- storage memory between DMA and MDMA engines.
- The region should be defined as child node of the AHB SRAM node
- as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml
+ maxItems: 1
+ description:
+ SRAM region which is used as temporary storage memory between DMA and
+ MDMA engines.
power-domains:
maxItems: 1
--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sram/sram-consumer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SRAM Consumers
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+select: true
+
+properties:
+ sram:
+ description:
+ Phandles to one or more reserved on-chip SRAM regions. The regions
+ should be defined as child nodes of the respective SRAM node, and
+ should be defined as per the generic bindings in,
+ Documentation/devicetree/bindings/sram/sram.yaml
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
+
+additionalProperties: true
+...
projects / thirdparty / linux.git / commitdiff
