drm/amdgpu: Fix JPEG v4.0.3 register write

[ Upstream commit 8c50bf9beb889fd2bdcbf95b27a5d101eede51fc ]

EXTERNAL_REG_INTERNAL_OFFSET/EXTERNAL_REG_WRITE_ADDR should be used in
pairs. If an external register shouldn't be written, both packets
shouldn't be sent.

Fixes: a78b48146972 ("drm/amdgpu: Skip PCTL0_MMHUB_DEEPSLEEP_IB write in jpegv4.0.3 under SRIOV")
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index b55041f38cec9b81ab2ae63c9ea769e70305921d..0dbc16ec25c82ac69da432d5a9349110af3fef22 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -668,11 +668,12 @@ void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring)
                amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
                        0, 0, PACKETJ_TYPE0));
                amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
-       }
 
-       amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
-               0, 0, PACKETJ_TYPE0));
-       amdgpu_ring_write(ring, 0x80004000);
+               amdgpu_ring_write(ring,
+                                 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0,
+                                         0, PACKETJ_TYPE0));
+               amdgpu_ring_write(ring, 0x80004000);
+       }
 }
 
 /**
@@ -688,11 +689,12 @@ void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring)
                amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
                        0, 0, PACKETJ_TYPE0));
                amdgpu_ring_write(ring, 0x62a04);
-       }
 
-       amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
-               0, 0, PACKETJ_TYPE0));
-       amdgpu_ring_write(ring, 0x00004000);
+               amdgpu_ring_write(ring,
+                                 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0,
+                                         0, PACKETJ_TYPE0));
+               amdgpu_ring_write(ring, 0x00004000);
+       }
 }
 
 /**