fsl-ddr: Add extra cycle to turnaround times

Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 03f9c4380d4435c7abba85ecc59a215a88cc774e..4a282bc52d8df9fe2d4bebb61782530dd12961df 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -198,6 +198,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
        pre_pd_exit_mclk = act_pd_exit_mclk;
        taxpd_mclk = 8;
        tmrd_mclk = 4;
+       /* set the turnaround time */
+       trwt_mclk = 1;
 #else /* CONFIG_FSL_DDR2 */
        /*
         * (tXARD and tXARDS). Empirical?