return TLBRET_NOMATCH;
}
-static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, target_ulong dmw)
+static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, uint64_t dmw)
{
if (is_la64(env)) {
return va & TARGET_VIRT_MASK;
uint32_t level, uint32_t mem_idx)
{
CPUState *cs = env_cpu(env);
- target_ulong badvaddr, index, phys;
+ uint64_t badvaddr;
+ target_ulong index, phys;
uint64_t dir_base, dir_width;
if (unlikely((level == 0) || (level > 4))) {
uint32_t mem_idx)
{
CPUState *cs = env_cpu(env);
- target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1, badv;
+ target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1;
+ uint64_t badv;
uint64_t ptbase = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);
uint64_t ptwidth = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH);
uint64_t dir_base, dir_width;