]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/msm/dsi: correct programming sequence for SM8350 / SM8450
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Sun, 4 Aug 2024 05:40:07 +0000 (08:40 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 4 Oct 2024 14:32:46 +0000 (16:32 +0200)
[ Upstream commit 1328cb7c34bf6d056df9ff694ee5194537548258 ]

According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have
different boundaries for pll_clock_inverters programming. Follow the
vendor code and use correct values.

Fixes: 2f9ae4e395ed ("drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/606947/
Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-3-1149dd8399fe@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

index 82d015aa2d634cc8706b1db6e6d3786634beeea1..29aa91238bc47e575bf6575e5a49f5289b06ecd5 100644 (file)
@@ -135,7 +135,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
                        config->pll_clock_inverters = 0x00;
                else
                        config->pll_clock_inverters = 0x40;
-       } else {
+       } else if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
                if (pll_freq <= 1000000000ULL)
                        config->pll_clock_inverters = 0xa0;
                else if (pll_freq <= 2500000000ULL)
@@ -144,6 +144,16 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
                        config->pll_clock_inverters = 0x00;
                else
                        config->pll_clock_inverters = 0x40;
+       } else {
+               /* 4.2, 4.3 */
+               if (pll_freq <= 1000000000ULL)
+                       config->pll_clock_inverters = 0xa0;
+               else if (pll_freq <= 2500000000ULL)
+                       config->pll_clock_inverters = 0x20;
+               else if (pll_freq <= 3500000000ULL)
+                       config->pll_clock_inverters = 0x00;
+               else
+                       config->pll_clock_inverters = 0x40;
        }
 
        config->decimal_div_start = dec;