drm/amd/display: External panel replay fsm control

[WHY]
To correctly control external panel replay fsm.

[HOW]
1. External panel replay is 1-A option only now.
2. Update cursor update and dirty rects commands for external
panel replay support.
3. Add external panel replay support flag in dc.

Reviewed-by: Robin Chen <robin.chen@amd.com>
Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index cb85b7ac2697bef597eba81bf075a9ac4a5ae03a..4305691ba45e638e7bde184e074efc50e4295296 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3860,7 +3860,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
        if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
                return;
 
-       if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
+       if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
                return;
 
        memset(&cmd, 0x0, sizeof(cmd));
@@ -3880,7 +3880,11 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
                if (srf_updates[i].surface->flip_immediate)
                        continue;
 
-               update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+               if (dc->config.frame_update_cmd_version2)
+                       update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2;
+               else
+                       update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
+
                update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
                memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
                                sizeof(flip_addr->dirty_rects));
@@ -3894,6 +3898,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 
                        update_dirty_rect->panel_inst = panel_inst;
                        update_dirty_rect->pipe_idx = j;
+                       update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
                        dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
                }
        }
@@ -3916,7 +3921,7 @@ static void build_dmub_update_dirty_rect(
        if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
                return;
 
-       if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
+       if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
                return;
 
        memset(&cmd, 0x0, sizeof(cmd));
@@ -3935,7 +3940,12 @@ static void build_dmub_update_dirty_rect(
                /* Do not send in immediate flip mode */
                if (srf_updates[i].surface->flip_immediate)
                        continue;
-               update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+
+               if (dc->config.frame_update_cmd_version2)
+                       update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2;
+               else
+                       update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
+
                update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
                memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
                                sizeof(flip_addr->dirty_rects));
@@ -3948,6 +3958,7 @@ static void build_dmub_update_dirty_rect(
                                continue;
                        update_dirty_rect->panel_inst = panel_inst;
                        update_dirty_rect->pipe_idx = j;
+                       update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
                        dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
                        dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
                        (*dmub_cmd_count)++;

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ab19b62309450e190a5c9b083c605e8089cfc302..ce2eceba2ab7c4e272330f70c79615eafd378a59 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -560,6 +560,7 @@ struct dc_config {
        bool enable_dpia_pre_training;
        bool unify_link_enc_assignment;
        bool enable_cursor_offload;
+       bool frame_update_cmd_version2;
        struct spl_sharpness_range dcn_sharpness_range;
        struct spl_sharpness_range dcn_override_sharpness_range;
 };

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index dc1b3f6c22c9679d57be36026fa87b5397878b57..e4dd5ca7098774d39a552874bb623ac24bfd5ed9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1034,12 +1034,19 @@ static void dc_build_cursor_update_payload0(
                struct pipe_ctx *pipe_ctx, uint8_t p_idx,
                struct dmub_cmd_update_cursor_payload0 *payload)
 {
+       struct dc *dc = pipe_ctx->stream->ctx->dc;
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
        unsigned int panel_inst = 0;
 
-       if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
-               pipe_ctx->stream->link, &panel_inst))
-               return;
+       if (dc->config.frame_update_cmd_version2 == true) {
+               /* Don't need panel_inst for command version2 */
+               payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2;
+       } else {
+               if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
+                       pipe_ctx->stream->link, &panel_inst))
+                       return;
+               payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
+       }
 
        /* Payload: Cursor Rect is built from position & attribute
         * x & y are obtained from postion
@@ -1052,8 +1059,8 @@ static void dc_build_cursor_update_payload0(
 
        payload->enable      = hubp->pos.cur_ctl.bits.cur_enable;
        payload->pipe_idx    = p_idx;
-       payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
        payload->panel_inst  = panel_inst;
+       payload->otg_inst    = pipe_ctx->stream_res.tg->inst;
 }
 
 static void dc_build_cursor_position_update_payload0(

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 0e953059ff6d8bca389c1c6d8ddbf61e0003f69e..2e38b6840c711011f62af2d1105964a1d25dd231 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1230,7 +1230,7 @@ struct replay_settings {
        uint32_t replay_desync_error_fail_count;
        /* The frame skip number dal send to DMUB */
        uint16_t frame_skip_number;
-       /* Current Panel Replay event */
+       /* Current Panel Replay events */
        uint32_t replay_events;
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
index bbd6f93f5c9818c6b288845d1f9efba07c529296..cc3b44cf76626f78f0bcad8ecdee1224aceb17bb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
@@ -35,6 +35,46 @@
 
 #define DP_SINK_PR_ENABLE_AND_CONFIGURATION            0x37B
 
+static unsigned int dp_pr_calc_num_static_frames(unsigned int vsync_rate_hz)
+{
+       // at least 2 frames for static screen
+       unsigned int num_frames = 2;
+
+       // get number of frames for at least 50ms
+       if (vsync_rate_hz > 40)
+               num_frames = (vsync_rate_hz + 10) / 20;
+
+       return num_frames;
+}
+
+static void dp_pr_set_static_screen_param(struct dc_link *link)
+{
+       struct dc_static_screen_params params = {0};
+       struct dc *dc = link->ctx->dc;
+       // only support DP sst for now
+       if (!dc_is_dp_sst_signal(link->connector_signal))
+               return;
+
+       for (int i = 0; i < MAX_PIPES; i++) {
+               if (dc->current_state->res_ctx.pipe_ctx[i].stream &&
+                       dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
+                       struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;
+                       unsigned int vsync_rate_hz = div64_u64(div64_u64(
+                                                                                       (stream->timing.pix_clk_100hz * (u64)100),
+                                                                                       stream->timing.v_total),
+                                                                                       stream->timing.h_total);
+
+                       params.triggers.cursor_update = true;
+                       params.triggers.overlay_update = true;
+                       params.triggers.surface_update = true;
+                       params.num_frames = dp_pr_calc_num_static_frames(vsync_rate_hz);
+
+                       dc_stream_set_static_screen_params(dc, &stream, 1, &params);
+                       break;
+               }
+       }
+}
+
 static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream)
 {
        /* To-do: Setup Replay */
@@ -159,6 +199,9 @@ bool dp_pr_get_panel_inst(const struct dc *dc,
        if (!dc || !link || !inst_out)
                return false;
 
+       if (dc->config.frame_update_cmd_version2 == false)
+               return dc_get_edp_link_panel_inst(dc, link, inst_out);
+
        if (!dc_is_dp_sst_signal(link->connector_signal)) /* only supoprt DP sst (eDP included) for now */
                return false;
 
@@ -199,6 +242,9 @@ bool dp_pr_enable(struct dc_link *link, bool enable)
        if (!dp_pr_get_panel_inst(dc, link, &panel_inst))
                return false;
 
+       if (enable && !dc_is_embedded_signal(link->connector_signal))
+               dp_pr_set_static_screen_param(link);
+
        if (link->replay_settings.replay_allow_active != enable) {
                //for sending PR enable commands to DMUB
                memset(&cmd, 0, sizeof(cmd));
@@ -276,6 +322,12 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con
                        pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) /
                        pipe_ctx->stream->timing.dsc_cfg.num_slices_v;
 
+       if (dc_is_embedded_signal(link->connector_signal))
+               cmd.pr_copy_settings.data.main_link_activity_option = 0x03;//OPTION_1C;
+       else
+               // For external DP, use option 1-A
+               cmd.pr_copy_settings.data.main_link_activity_option = 0x01;//OPTION_1A;
+
        dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
        return true;
 }