clk: qcom: gcc-ipq6018: rework nss_port5 clock to multiple conf

[ Upstream commit 2f7b168323c22faafb1fbf94ef93b7ce5efc15c6 ]

Rework nss_port5 to use the new multiple configuration implementation
and correctly fix the clocks for this port under some corner case.

In OpenWrt, this patch avoids intermittent dmesg errors of the form
nss_port5_rx_clk_src: rcg didn't update its configuration.

This is a mechanical, straightforward port of
commit e88f03230dc07aa3293b6aeb078bd27370bb2594
("clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf")
to gcc-ipq6018, with two conflicts resolved: different frequency of the
P_XO clock source, and only 5 Ethernet ports.

This was originally developed by JiaY-shi <shi05275@163.com>.

Link: https://lore.kernel.org/all/20231220221724.3822-4-ansuelsmth@gmail.com/
Signed-off-by: Marko Mäkelä <marko.makela@iki.fi>
Tested-by: Marko Mäkelä <marko.makela@iki.fi>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250802095546.295448-1-marko.makela@iki.fi
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index ab0f7fc665a9790dd8edba0cf4b86c5c672a337d..c04a7a961a24a0e9afe316b7ae6c92789ed7bcf8 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -511,15 +511,23 @@ static struct clk_rcg2 apss_ahb_clk_src = {
        },
 };
 
-static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
-       F(24000000, P_XO, 1, 0, 0),
-       F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
-       F(25000000, P_UNIPHY0_RX, 5, 0, 0),
-       F(78125000, P_UNIPHY1_RX, 4, 0, 0),
-       F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
-       F(125000000, P_UNIPHY0_RX, 1, 0, 0),
-       F(156250000, P_UNIPHY1_RX, 2, 0, 0),
-       F(312500000, P_UNIPHY1_RX, 1, 0, 0),
+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
+       C(P_UNIPHY1_RX, 12.5, 0, 0),
+       C(P_UNIPHY0_RX, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
+       C(P_UNIPHY1_RX, 2.5, 0, 0),
+       C(P_UNIPHY0_RX, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
+       FMS(24000000, P_XO, 1, 0, 0),
+       FM(25000000, ftbl_nss_port5_rx_clk_src_25),
+       FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
+       FM(125000000, ftbl_nss_port5_rx_clk_src_125),
+       FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
+       FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
        { }
 };
 
@@ -547,26 +555,34 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 
 static struct clk_rcg2 nss_port5_rx_clk_src = {
        .cmd_rcgr = 0x68060,
-       .freq_tbl = ftbl_nss_port5_rx_clk_src,
+       .freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
        .hid_width = 5,
        .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "nss_port5_rx_clk_src",
                .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
                .num_parents = 7,
-               .ops = &clk_rcg2_ops,
+               .ops = &clk_rcg2_fm_ops,
        },
 };
 
-static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
-       F(24000000, P_XO, 1, 0, 0),
-       F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
-       F(25000000, P_UNIPHY0_TX, 5, 0, 0),
-       F(78125000, P_UNIPHY1_TX, 4, 0, 0),
-       F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
-       F(125000000, P_UNIPHY0_TX, 1, 0, 0),
-       F(156250000, P_UNIPHY1_TX, 2, 0, 0),
-       F(312500000, P_UNIPHY1_TX, 1, 0, 0),
+static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
+       C(P_UNIPHY1_TX, 12.5, 0, 0),
+       C(P_UNIPHY0_TX, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
+       C(P_UNIPHY1_TX, 2.5, 0, 0),
+       C(P_UNIPHY0_TX, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
+       FMS(24000000, P_XO, 1, 0, 0),
+       FM(25000000, ftbl_nss_port5_tx_clk_src_25),
+       FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
+       FM(125000000, ftbl_nss_port5_tx_clk_src_125),
+       FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
+       FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
        { }
 };
 
@@ -594,14 +610,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 
 static struct clk_rcg2 nss_port5_tx_clk_src = {
        .cmd_rcgr = 0x68068,
-       .freq_tbl = ftbl_nss_port5_tx_clk_src,
+       .freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
        .hid_width = 5,
        .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "nss_port5_tx_clk_src",
                .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
                .num_parents = 7,
-               .ops = &clk_rcg2_ops,
+               .ops = &clk_rcg2_fm_ops,
        },
 };