drm/i915/wm: Modify latency programmed into PKG_C_LATENCY

Increase the latency programmed into PKG_C_LATENCY latency to be
a multiple of line time which is written into WM_LINETIME.

--v2
-Fix commit subject line [Sai Teja]
-Use individual DISPLAY_VER checks instead of range [Sai Teja]
-Initialize max_linetime [Sai Teja]

--v3
-take into account the scenario when adjusted_latency is 0 [Vinod]

--v4
-rename adjusted_latency to latency [Mitul]
-fix the condition in which dpkgc is disabled [Vinod]

--v5
-Add check to see if max_linetime is 0 [Vinod]

--v6
-Avoid nested if statements [Mitul]

WA: 22020299601
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241203084706.2126189-5-suraj.kandpal@intel.com

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 95b306c229542f484965644aaa1fe6b980f6cb11..4c032b1758e7738bdb3641bf5a4f3814039cf283 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2861,7 +2861,8 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state)
        struct drm_i915_private *i915 = to_i915(display->drm);
        struct intel_crtc *crtc;
        struct intel_crtc_state *new_crtc_state;
-       u32 max_latency = LNL_PKG_C_LATENCY_MASK;
+       u32 latency = LNL_PKG_C_LATENCY_MASK;
+       u32 max_linetime = 0;
        u32 clear, val;
        u32 added_wake_time = 0;
        bool fixed_refresh_rate = false;
@@ -2875,18 +2876,26 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state)
                    (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
                     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
                        fixed_refresh_rate = true;
+
+               max_linetime = max(new_crtc_state->linetime, max_linetime);
        }
 
        if (fixed_refresh_rate) {
-               max_latency = skl_watermark_max_latency(i915, 1);
-               if (max_latency == 0)
-                       max_latency = LNL_PKG_C_LATENCY_MASK;
+               latency = skl_watermark_max_latency(i915, 1);
+               /* Wa_22020299601 */
+               if ((latency && max_linetime) &&
+                   (DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30)) {
+                       latency = max_linetime * DIV_ROUND_UP(latency, max_linetime);
+               } else if (!latency) {
+                       latency = LNL_PKG_C_LATENCY_MASK;
+               }
+
                added_wake_time = DSB_EXE_TIME +
                        display->sagv.block_time_us;
        }
 
        clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
-       val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
+       val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency) |
                REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
 
        intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val);