wifi: ath12k: Enable filter config for monitor destination ring

Add provision to configure monitor filter for the destination
ring. These filters are used for requesting statistics or monitor mode
through the monitor destination ring.

Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.3.1-00173-QCAHKSWPL_SILICONZ-1
Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3

Signed-off-by: P Praneesh <quic_ppranees@quicinc.com>
Link: https://patch.msgid.link/20241223060132.3506372-3-quic_ppranees@quicinc.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>

diff --git a/drivers/net/wireless/ath/ath12k/dp.h b/drivers/net/wireless/ath/ath12k/dp.h
index 1099ec19260bb571a10a642c5b586ab1c3b93f52..6946fb4f5c25f5a7ec5dbb27d40d09094380557a 100644 (file)
--- a/drivers/net/wireless/ath/ath12k/dp.h
+++ b/drivers/net/wireless/ath/ath12k/dp.h
@@ -770,8 +770,22 @@ enum htt_stats_internal_ppdu_frametype {
 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID    GENMASK(23, 16)
 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS         BIT(24)
 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS         BIT(25)
-#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE   GENMASK(15, 0)
-#define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID      BIT(26)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID       BIT(26)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL     BIT(27)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON           BIT(28)
+
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE           GENMASK(15, 0)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT      GENMASK(18, 16)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL      GENMASK(21, 19)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA      GENMASK(24, 22)
+
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD     GENMASK(9, 0)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE   BIT(17)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE       BIT(18)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE   BIT(19)
+
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET  BIT(0)
+#define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET     GENMASK(14, 1)
 
 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET      GENMASK(15, 0)
 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET      GENMASK(31, 16)
@@ -800,6 +814,7 @@ enum htt_rx_filter_tlv_flags {
        HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS     = BIT(10),
        HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
        HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE    = BIT(12),
+       HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO    = BIT(13),
 };
 
 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
@@ -1088,6 +1103,21 @@ enum htt_rx_data_pkt_filter_tlv_flasg3 {
                HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
                HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
 
+#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING \
+       (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
+       HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
+       HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
+       HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
+       HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
+       HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
+       HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
+       HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
+       HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
+       HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
+       HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
+       HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE | \
+       HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO)
+
 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */
 #define HTT_RX_TLV_FLAGS_RXDMA_RING \
                (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
@@ -1116,6 +1146,10 @@ struct htt_rx_ring_selection_cfg_cmd {
        __le32 info3;
 } __packed;
 
+#define HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE   32
+#define HTT_RX_RING_DEFAULT_DMA_LENGTH         0x7
+#define HTT_RX_RING_PKT_TLV_OFFSET             0x1
+
 struct htt_rx_ring_tlv_filter {
        u32 rx_filter; /* see htt_rx_filter_tlv_flags */
        u32 pkt_filter_flags0; /* MGMT */
@@ -1133,6 +1167,17 @@ struct htt_rx_ring_tlv_filter {
        u16 rx_mpdu_start_wmask;
        u16 rx_mpdu_end_wmask;
        u32 rx_msdu_end_wmask;
+       u32 conf_len_ctrl;
+       u32 conf_len_mgmt;
+       u32 conf_len_data;
+       u16 rx_drop_threshold;
+       bool enable_log_mgmt_type;
+       bool enable_log_ctrl_type;
+       bool enable_log_data_type;
+       bool enable_rx_tlv_offset;
+       u16 rx_tlv_offset;
+       bool drop_threshold_valid;
+       bool rxmon_disable;
 };
 
 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT  0x0

diff --git a/drivers/net/wireless/ath/ath12k/dp_tx.c b/drivers/net/wireless/ath/ath12k/dp_tx.c
index 133a496bebb9771adef057898d34fb8b461b9209..aa8058dd2da625a5be830c54b354bff46eb54cbe 100644 (file)
--- a/drivers/net/wireless/ath/ath12k/dp_tx.c
+++ b/drivers/net/wireless/ath/ath12k/dp_tx.c
@@ -1209,15 +1209,46 @@ int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id,
        cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
                                       HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS);
        cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid,
-                                      HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID);
+                                      HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID);
+       cmd->info0 |=
+               le32_encode_bits(tlv_filter->drop_threshold_valid,
+                                HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL);
+       cmd->info0 |= le32_encode_bits(!tlv_filter->rxmon_disable,
+                                      HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON);
+
        cmd->info1 = le32_encode_bits(rx_buf_size,
                                      HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE);
+       cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_mgmt,
+                                      HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);
+       cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_ctrl,
+                                      HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);
+       cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_data,
+                                      HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);
        cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0);
        cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1);
        cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2);
        cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3);
        cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter);
 
+       cmd->info2 = le32_encode_bits(tlv_filter->rx_drop_threshold,
+                                     HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD);
+       cmd->info2 |=
+               le32_encode_bits(tlv_filter->enable_log_mgmt_type,
+                                HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE);
+       cmd->info2 |=
+               le32_encode_bits(tlv_filter->enable_log_ctrl_type,
+                                HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE);
+       cmd->info2 |=
+               le32_encode_bits(tlv_filter->enable_log_data_type,
+                                HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE);
+
+       cmd->info3 =
+               le32_encode_bits(tlv_filter->enable_rx_tlv_offset,
+                                HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET);
+       cmd->info3 |=
+               le32_encode_bits(tlv_filter->rx_tlv_offset,
+                                HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET);
+
        if (tlv_filter->offset_valid) {
                cmd->rx_packet_offset =
                        le32_encode_bits(tlv_filter->rx_packet_offset,
@@ -1342,15 +1373,28 @@ int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset)
 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset)
 {
        struct ath12k_base *ab = ar->ab;
-       struct ath12k_dp *dp = &ab->dp;
        struct htt_rx_ring_tlv_filter tlv_filter = {0};
-       int ret, ring_id;
+       int ret, ring_id, i;
 
-       ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
        tlv_filter.offset_valid = false;
 
        if (!reset) {
-               tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
+               tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING;
+
+               tlv_filter.drop_threshold_valid = true;
+               tlv_filter.rx_drop_threshold = HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE;
+
+               tlv_filter.enable_log_mgmt_type = true;
+               tlv_filter.enable_log_ctrl_type = true;
+               tlv_filter.enable_log_data_type = true;
+
+               tlv_filter.conf_len_ctrl = HTT_RX_RING_DEFAULT_DMA_LENGTH;
+               tlv_filter.conf_len_mgmt = HTT_RX_RING_DEFAULT_DMA_LENGTH;
+               tlv_filter.conf_len_data = HTT_RX_RING_DEFAULT_DMA_LENGTH;
+
+               tlv_filter.enable_rx_tlv_offset = true;
+               tlv_filter.rx_tlv_offset = HTT_RX_RING_PKT_TLV_OFFSET;
+
                tlv_filter.pkt_filter_flags0 =
                                        HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
                                        HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
@@ -1368,14 +1412,19 @@ int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset)
        }
 
        if (ab->hw_params->rxdma1_enable) {
-               ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0,
-                                                      HAL_RXDMA_MONITOR_BUF,
-                                                      DP_RXDMA_REFILL_RING_SIZE,
-                                                      &tlv_filter);
-               if (ret) {
-                       ath12k_err(ab,
-                                  "failed to setup filter for monitor buf %d\n", ret);
-                       return ret;
+               for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
+                       ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id;
+                       ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
+                                                              ar->dp.mac_id + i,
+                                                              HAL_RXDMA_MONITOR_DST,
+                                                              DP_RXDMA_REFILL_RING_SIZE,
+                                                              &tlv_filter);
+                       if (ret) {
+                               ath12k_err(ab,
+                                          "failed to setup filter for monitor buf %d\n",
+                                          ret);
+                               return ret;
+                       }
                }
        }