riscv: dts: microchip: update pcie reg properties to new format

The existing PolarFire SoC devicetrees all use root port instance 1,
update the reg properties in PCIe nodes to use the new format that
specifies the instance in use. Failing to do so would still work but
produces warnings:
mpfs-icicle-kit.dtb: pcie@3000000000: reg: [[48, 0, 0, 134217728], [0, 1124073472, 0, 65536]] is too short
mpfs-icicle-kit.dtb: pcie@3000000000: reg-names: ['cfg', 'apb'] is too short

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Conor Dooley <conor@kernel.org>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: valentina.fernandezalanis@microchip.com
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 1069134f2e12ab7f622d5f618a85a5eafb0511f1..a6dda55a2d1ddbdbb6ae5b5cc0a5ba25aaef618e 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -32,8 +32,9 @@
                #interrupt-cells = <0x1>;
                #size-cells = <0x2>;
                device_type = "pci";
-               reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
-               reg-names = "cfg", "apb";
+               reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
+                     <0x0 0x4300a000 0x0 0x2000>;
+               reg-names = "cfg", "bridge", "ctrl";
                bus-range = <0x0 0x7f>;
                interrupt-parent = <&plic>;
                interrupts = <119>;

diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
index 8230f06ddf48a6e3c7178f1b43cbffdec1d651cb..36a9860f31dacbdae6fc25b0176f134441563575 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
@@ -20,8 +20,9 @@
                #interrupt-cells = <0x1>;
                #size-cells = <0x2>;
                device_type = "pci";
-               reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
-               reg-names = "cfg", "apb";
+               reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
+                     <0x0 0x4300a000 0x0 0x2000>;
+               reg-names = "cfg", "bridge", "ctrl";
                bus-range = <0x0 0x7f>;
                interrupt-parent = <&plic>;
                interrupts = <119>;

diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
index 9a56de7b91d64c48ebaea95daaba794a6822e729..a57dca891965a62810d4bc2df1ad6736362b260f 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -20,8 +20,9 @@
                #interrupt-cells = <0x1>;
                #size-cells = <0x2>;
                device_type = "pci";
-               reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
-               reg-names = "cfg", "apb";
+               reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
+                     <0x0 0x4300a000 0x0 0x2000>;
+               reg-names = "cfg", "bridge", "ctrl";
                bus-range = <0x0 0x7f>;
                interrupt-parent = <&plic>;
                interrupts = <119>;