Bool dis_P6 ( UInt theInstr,
Bool allow_F, Bool allow_V, Bool allow_FX, Bool allow_GX)
{
- /* This is a hack. We should do P6 capability checking properly.
- But anyway, make a guess at whether we should even try to handle
- this instruction. All P6 capable CPUs should be able to handle
- F, V, FX and GX, so that seems like a good check. */
+ UInt opc, rd, ra, rb, opc2, dot;
+
+ /* This is a hack. We should do P6 capability checking properly.
+ But anyway, make a guess at whether we should even try to handle
+ this instruction. All P6 capable CPUs should be able to handle
+ F, V, FX and GX, so that seems like a good check. */
if (! (allow_F && allow_V && allow_FX && allow_GX) )
return False;
if (!mode64)
return False; /* only support P6 in 64-bit mode for now */
- UInt opc = ifieldOPC(theInstr); /* primary opcode */
- UInt rd = ifieldRegDS(theInstr); /* dst reg */
- UInt ra = ifieldRegA(theInstr); /* first source reg */
- UInt rb = ifieldRegB(theInstr); /* second source reg */
- UInt opc2 = ifieldOPClo10(theInstr); /* secondary opc, 10:1 */
- UInt dot = ifieldBIT0(theInstr); /* Rc field, bit 0 */
+ opc = ifieldOPC(theInstr); /* primary opcode */
+ rd = ifieldRegDS(theInstr); /* dst reg */
+ ra = ifieldRegA(theInstr); /* first source reg */
+ rb = ifieldRegB(theInstr); /* second source reg */
+ opc2 = ifieldOPClo10(theInstr); /* secondary opc, 10:1 */
+ dot = ifieldBIT0(theInstr); /* Rc field, bit 0 */
if (opc == 63 && ra == 0/*presumably*/ && opc2 == 488) {
/* frim (Floating Round to Integer Minus, PPC ISA 2.05 p137) */