Transfer timeouts are currently measured from the point where a transfer
list is queued to the controller. This can cause transfers to time out
before they have actually started, if earlier queued transfers consume
the timeout interval.
Fix this by recording when a transfer reaches the head of the queue and
adjusting the timeout calculation to start from that point. The existing
low-overhead completion-based timeout mechanism is preserved, but care is
taken to ensure the transfer start time is consistently recorded for both
PIO and DMA paths.
This prevents premature timeouts while retaining efficient timeout
handling.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260603090754.16252-16-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
{
struct completion *done = xfer[n - 1].completion;
unsigned long timeout = xfer[n - 1].timeout;
+ unsigned long remaining_timeout = timeout;
+ long time_taken;
+ bool started;
int ret;
+ xfer[0].started = false;
+
ret = hci->io->queue_xfer(hci, xfer, n);
if (ret)
return ret;
- if (!wait_for_completion_timeout(done, timeout)) {
+ while (!wait_for_completion_timeout(done, remaining_timeout)) {
+ scoped_guard(spinlock_irqsave, &hci->lock) {
+ started = xfer[0].started;
+ time_taken = jiffies - xfer[0].start_jiffies;
+ }
+ /* Keep waiting if xfer has not started */
+ if (!started)
+ continue;
+ /* Recalculate timeout based on actual start time */
+ if (time_taken < timeout) {
+ remaining_timeout = timeout - time_taken;
+ continue;
+ }
if (hci->io->dequeue_xfer(hci, xfer, n)) {
dev_err(&hci->master.dev, "%s: timeout error\n", __func__);
return -ETIMEDOUT;
enqueue_ptr = (enqueue_ptr + 1) % rh->xfer_entries;
}
+ if (rh->xfer_space == rh->xfer_entries)
+ hci_start_xfer(xfer_list);
+
rh->xfer_space -= n;
op1_val &= ~RING_OP1_CR_ENQ_PTR;
u32 op1_val, op2_val, resp, *ring_resp;
unsigned int tid, done_ptr = rh->done_ptr;
unsigned int done_cnt = 0;
+ bool start_next = false;
struct hci_xfer *xfer;
for (;;) {
xfer->response = resp;
if (xfer == xfer->final_xfer || RESP_STATUS(resp))
complete(xfer->final_xfer->completion);
- if (RESP_STATUS(resp))
+ else
+ hci_start_xfer(xfer);
+ if (RESP_STATUS(resp)) {
hci->enqueue_blocked = true;
+ start_next = false;
+ } else {
+ start_next = true;
+ }
}
done_ptr = (done_ptr + 1) % rh->xfer_entries;
}
rh->xfer_space += done_cnt;
+ if (start_next && rh->xfer_space < rh->xfer_entries) {
+ xfer = rh->src_xfers[done_ptr];
+ hci_start_xfer(xfer);
+ }
op1_val = rh_reg_read(RING_OPERATION1);
op1_val &= ~RING_OP1_CR_SW_DEQ_PTR;
op1_val |= FIELD_PREP(RING_OP1_CR_SW_DEQ_PTR, done_ptr);
hci_dma_unblock_enqueue(hci);
+ if (rh->xfer_space < rh->xfer_entries)
+ hci_start_xfer(rh->src_xfers[rh->done_ptr]);
+
spin_unlock_irq(&hci->lock);
wait_for_completion_timeout(&rh->op_done, HZ);
#define HCI_H
#include <linux/io.h>
+#include <linux/jiffies.h>
/* 32-bit word aware bit and mask macros */
#define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0)
u32 cmd_desc[4];
u32 response;
bool rnw;
+ bool started;
void *data;
unsigned int data_len;
unsigned int cmd_tid;
struct completion *completion;
unsigned long timeout;
+ unsigned long start_jiffies;
union {
struct {
/* PIO specific */
kfree(xfer);
}
+static inline void hci_start_xfer(struct hci_xfer *xfer)
+{
+ if (!xfer->started) {
+ xfer->started = true;
+ xfer->start_jiffies = jiffies;
+ }
+}
+
/* This abstracts PIO vs DMA operations */
struct hci_io_ops {
bool (*irq_handler)(struct i3c_hci *hci);
* Finally send the command.
*/
hci_pio_write_cmd(hci, pio->curr_xfer);
+ hci_start_xfer(pio->curr_xfer);
/*
* And move on.
*/