#define USE_DLY_MAX_SMPL (14)
struct k3_priv {
- int ctrl_id;
u32 cur_speed;
struct regmap *reg;
};
if (IS_ERR(priv->reg))
priv->reg = NULL;
- priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
- if (priv->ctrl_id < 0)
- priv->ctrl_id = 0;
-
- if (priv->ctrl_id >= TIMING_MODE)
- return -EINVAL;
-
host->priv = priv;
return 0;
}
.execute_tuning = dw_mci_hi6220_execute_tuning,
};
-static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
+static int dw_mci_hs_set_timing(struct dw_mci *host, int timing,
int smpl_phase)
{
u32 drv_phase;
u32 enable_shift = 0;
u32 reg_value;
int ctrl_id;
- struct k3_priv *priv;
- priv = host->priv;
- ctrl_id = priv->ctrl_id;
+ ctrl_id = host->mmc->index;
+ if (ctrl_id >= TIMING_MODE)
+ return -EINVAL;
drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly;
/* We should delay 1ms wait for timing setting finished. */
usleep_range(1000, 2000);
+
+ return 0;
}
static int dw_mci_hi3660_init(struct dw_mci *host)
mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD,
SDMMC_CARD_RD_THR_EN));
- dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1);
host->bus_hz /= (GENCLK_DIV + 1);
- return 0;
+ return dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1);
}
static int dw_mci_set_sel18(struct dw_mci *host, bool set)
if (!priv || !priv->reg)
return 0;
- if (priv->ctrl_id == DWMMC_SDIO_ID)
+ if (mmc->index == DWMMC_SDIO_ID)
return 0;
if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)