]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
vect: Fix vect_is_reduction
authorRichard Sandiford <richard.sandiford@arm.com>
Tue, 30 Nov 2021 09:52:27 +0000 (09:52 +0000)
committerRichard Sandiford <richard.sandiford@arm.com>
Tue, 30 Nov 2021 09:52:27 +0000 (09:52 +0000)
The current definition of vect_is_reduction (provided for target
costing) misses some pattern statements.

gcc/
* tree-vectorizer.h (vect_is_reduction): Use STMT_VINFO_REDUC_IDX.

gcc/testsuite/
* gcc.target/aarch64/sve/cost_model_13.c: New test.

gcc/testsuite/gcc.target/aarch64/sve/cost_model_13.c [new file with mode: 0644]
gcc/tree-vectorizer.h

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_13.c b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_13.c
new file mode 100644 (file)
index 0000000..95f2ce9
--- /dev/null
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -mtune=neoverse-v1" } */
+
+int
+f11 (short *restrict x, int n)
+{
+  short res = 0;
+  for (int i = 0; i < n; ++i)
+    res += x[i];
+  return res;
+}
+
+/* We should use SVE rather than Advanced SIMD.  */
+/* { dg-final { scan-assembler {\tld1h\tz[0-9]+\.h,} } } */
+/* { dg-final { scan-assembler {\tadd\tz[0-9]+\.h,} } } */
+/* { dg-final { scan-assembler-not {\tldr\tq[0-9]+,} } } */
+/* { dg-final { scan-assembler-not {\tv[0-9]+\.8h,} } } */
index 0eb13d6cc74fc70272f3c9cdaa018252817bf2de..76e81ea546ad4ac75572c1311a8284f96249b497 100644 (file)
@@ -2372,8 +2372,7 @@ vect_is_store_elt_extraction (vect_cost_for_stmt kind, stmt_vec_info stmt_info)
 inline bool
 vect_is_reduction (stmt_vec_info stmt_info)
 {
-  return (STMT_VINFO_REDUC_DEF (stmt_info)
-         || VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE (stmt_info)));
+  return STMT_VINFO_REDUC_IDX (stmt_info) >= 0;
 }
 
 /* If STMT_INFO describes a reduction, return the vect_reduction_type