The current definition of vect_is_reduction (provided for target
costing) misses some pattern statements.
gcc/
* tree-vectorizer.h (vect_is_reduction): Use STMT_VINFO_REDUC_IDX.
gcc/testsuite/
* gcc.target/aarch64/sve/cost_model_13.c: New test.
--- /dev/null
+/* { dg-options "-O3 -mtune=neoverse-v1" } */
+
+int
+f11 (short *restrict x, int n)
+{
+ short res = 0;
+ for (int i = 0; i < n; ++i)
+ res += x[i];
+ return res;
+}
+
+/* We should use SVE rather than Advanced SIMD. */
+/* { dg-final { scan-assembler {\tld1h\tz[0-9]+\.h,} } } */
+/* { dg-final { scan-assembler {\tadd\tz[0-9]+\.h,} } } */
+/* { dg-final { scan-assembler-not {\tldr\tq[0-9]+,} } } */
+/* { dg-final { scan-assembler-not {\tv[0-9]+\.8h,} } } */
inline bool
vect_is_reduction (stmt_vec_info stmt_info)
{
- return (STMT_VINFO_REDUC_DEF (stmt_info)
- || VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE (stmt_info)));
+ return STMT_VINFO_REDUC_IDX (stmt_info) >= 0;
}
/* If STMT_INFO describes a reduction, return the vect_reduction_type