net: ena: set initial DMA width to avoid intel iommu issue

[ Upstream commit 09323b3bca95181c0da79daebc8b0603e500f573 ]

The ENA driver uses the readless mechanism, which uses DMA, to find
out what the DMA mask is supposed to be.

If DMA is used without setting the dma_mask first, it causes the
Intel IOMMU driver to think that ENA is a 32-bit device and therefore
disables IOMMU passthrough permanently.

This patch sets the dma_mask to be ENA_MAX_PHYS_ADDR_SIZE_BITS=48
before readless initialization in
ena_device_init()->ena_com_mmio_reg_read_request_init(),
which is large enough to workaround the intel_iommu issue.

DMA mask is set again to the correct value after it's received from the
device after readless is initialized.

The patch also changes the driver to use dma_set_mask_and_coherent()
function instead of the two pci_set_dma_mask() and
pci_set_consistent_dma_mask() ones. Both methods achieve the same
effect.

Fixes: 1738cd3ed342 ("net: ena: Add a driver for Amazon Elastic Network Adapters (ENA)")
Signed-off-by: Mike Cui <mikecui@amazon.com>
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
Signed-off-by: Shay Agroskin <shayagr@amazon.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
index 0a8520a2e46499b15b0a51f6a00b831a7973ebe7..1c978c7987adc808a1e70a16fbbf29fe7872864e 100644 (file)
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
@@ -3357,16 +3357,9 @@ static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
                goto err_mmio_read_less;
        }
 
-       rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width));
+       rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_width));
        if (rc) {
-               dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc);
-               goto err_mmio_read_less;
-       }
-
-       rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width));
-       if (rc) {
-               dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n",
-                       rc);
+               dev_err(dev, "dma_set_mask_and_coherent failed %d\n", rc);
                goto err_mmio_read_less;
        }
 
@@ -4136,6 +4129,12 @@ static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                return rc;
        }
 
+       rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(ENA_MAX_PHYS_ADDR_SIZE_BITS));
+       if (rc) {
+               dev_err(&pdev->dev, "dma_set_mask_and_coherent failed %d\n", rc);
+               goto err_disable_device;
+       }
+
        pci_set_master(pdev);
 
        ena_dev = vzalloc(sizeof(*ena_dev));