clk: imx: fracn-gppll: Add 332.60 MHz Support

Some parallel panels have a pixelclk of 33.260 MHz. Add support for
332.60 MHz so a by 10 divider can be used to derive the exact pixelclk.

Reviewed-by: Primoz Fiser <primoz.fiser@norik.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Daniel Baluta <daniel.baluta@nxp.com>
Link: https://patch.msgid.link/20260113-v6-18-topic-clk-fracn-gppll-v3-1-45da70f43c98@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 090d608672508a8819dc68eedec5b8d4a2c140c8..579f76494eb041dfba58b8cd10eb2453a0ec4178 100644 (file)
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -88,6 +88,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
        PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
        PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
        PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
+       PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
        PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
 };