GCN: Generally enable the 'gcc.target/gcn/avgpr-[...]' test cases

... added in commit ae0d2c240213c5a7f6959c032bfc9f0703cab787
"amdgcn: Add Accelerator VGPR registers".  This way, they're correctly tested
no matter what '-march=[...]' is used with 'make check'.

	gcc/testsuite/
	* gcc.target/gcn/avgpr-mem-double.c: Remove
	'dg-skip-if "incompatible ISA" [...]'.
	* gcc.target/gcn/avgpr-mem-int.c: Likewise.
	* gcc.target/gcn/avgpr-mem-long.c: Likewise.
	* gcc.target/gcn/avgpr-mem-short.c: Likewise.
	* gcc.target/gcn/avgpr-spill-double.c: Likewise.
	* gcc.target/gcn/avgpr-spill-int.c: Likewise.
	* gcc.target/gcn/avgpr-spill-long.c: Likewise.
	* gcc.target/gcn/avgpr-spill-short.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c
index ce089fb198d2e519a34339cbd6ee8d40b6e58051..34317a507157e063fbc0a265440f5a1aecddd2ea 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx90a -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
 /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
 /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */
 

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c
index 03d8148646641b64cdb4c0e9107e52dcd7d98ede..5ea3755e1b8f1e5d665c2ed931096625850692a4 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx90a -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
 /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
 /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */
 

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c
index dcfb483f3f3c8bfc62f6dd336304b3d4aeecff60..b52fc98da85b7ea00577705499089fd76a42ed19 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx90a -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
 /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
 /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */
 

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c
index 91cc14ef181bcfb48641d4cab09116fad9d87965..a3e4a8bf9a93506447174ce375ac0a9e545185be 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx90a -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */
 /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */
 /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */
 

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
index 3e9996d3d1023abe7606ac0b794350fa31801c3f..53853a4b0757bfcf50490a23a7ef27cc3ca183f0 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 #define TYPE double

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
index 0b64c8ec176c26192d3beb8da8ed4d189354d99d..650f1587a1bb5ddf91d6ea867b76d6c710f40931 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 #ifndef TYPE

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
index 516890de14c778b7f5dbe3184d4997b17134ad95..51f887c4d59e274d2087c5555424ca48a46d5d99 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 #define TYPE long

diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
index 1e556840e0f5f464fe7ad8a17fb61f7dc971ae65..983d2017ff5f2c953b536702b3b26ca14dca8a08 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
+++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c
@@ -1,6 +1,5 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=gfx908 -O1" } */
-/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */
 /* { dg-final { scan-assembler "accvgpr" } } */
 
 #define TYPE short