]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
wifi: rtw89: 8922d: add RF ops of init hardware and get thermal
authorPing-Ke Shih <pkshih@realtek.com>
Mon, 30 Mar 2026 06:58:44 +0000 (14:58 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Thu, 2 Apr 2026 03:18:40 +0000 (11:18 +0800)
One is to initialize hardware for RF circuit, and the ops of get thermal
is used to monitor temperature to re-calibrate RF or reduce TX duty to
prevent overheating.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260330065847.48946-7-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/reg.h
drivers/net/wireless/realtek/rtw89/rtw8922d.c
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.c
drivers/net/wireless/realtek/rtw89/rtw8922d_rfk.h

index 78f2cf579fa61419a262f86edbdfd33daa7335d9..e5e689f1bfa3de4237ef7657e71a60edc3a82c32 100644 (file)
 #define B_KTBL1_TBL0 BIT(3)
 #define B_KTBL1_TBL1 BIT(5)
 
+#define R_TC_EN_BE4 0x3c200
+#define B_TC_EN_BE4 BIT(0)
+#define B_TC_TRIG_BE4 BIT(1)
+#define R_TC_VAL_BE4 0x3c208
+#define B_TC_VAL_BE4 GENMASK(7, 0)
+
 /* WiFi CPU local domain */
 #define R_AX_WDT_CTRL 0x0040
 #define B_AX_WDT_EN BIT(31)
index cfe9752abddcb858be81d7fb30862ba9939eb994..49b84d49ccace29c71e228802cade0db51d15aa8 100644 (file)
@@ -2562,6 +2562,63 @@ static void rtw8922d_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
                                   &tx_en1, false);
 }
 
+static u8 rtw8922d_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
+{
+       u8 val;
+
+       rtw89_phy_write32_mask(rtwdev, R_TC_EN_BE4, B_TC_EN_BE4, 0x1);
+       rtw89_phy_write32_mask(rtwdev, R_TC_EN_BE4, B_TC_TRIG_BE4, 0x0);
+       rtw89_phy_write32_mask(rtwdev, R_TC_EN_BE4, B_TC_TRIG_BE4, 0x1);
+
+       fsleep(100);
+
+       val = rtw89_phy_read32_mask(rtwdev, R_TC_VAL_BE4, B_TC_VAL_BE4);
+
+       return val;
+}
+
+static u32 rtw8922d_chan_to_rf18_val(struct rtw89_dev *rtwdev,
+                                    const struct rtw89_chan *chan)
+{
+       u32 val = u32_encode_bits(chan->channel, RR_CFGCH_CH);
+
+       switch (chan->band_type) {
+       case RTW89_BAND_2G:
+       default:
+               break;
+       case RTW89_BAND_5G:
+               val |= u32_encode_bits(CFGCH_BAND1_5G, RR_CFGCH_BAND1) |
+                      u32_encode_bits(CFGCH_BAND0_5G, RR_CFGCH_BAND0);
+               break;
+       case RTW89_BAND_6G:
+               val |= u32_encode_bits(CFGCH_BAND1_6G, RR_CFGCH_BAND1) |
+                      u32_encode_bits(CFGCH_BAND0_6G, RR_CFGCH_BAND0);
+               break;
+       }
+
+       switch (chan->band_width) {
+       case RTW89_CHANNEL_WIDTH_5:
+       case RTW89_CHANNEL_WIDTH_10:
+       case RTW89_CHANNEL_WIDTH_20:
+       default:
+               break;
+       case RTW89_CHANNEL_WIDTH_40:
+               val |= u32_encode_bits(CFGCH_BW_V2_40M, RR_CFGCH_BW_V2);
+               break;
+       case RTW89_CHANNEL_WIDTH_80:
+               val |= u32_encode_bits(CFGCH_BW_V2_80M, RR_CFGCH_BW_V2);
+               break;
+       case RTW89_CHANNEL_WIDTH_160:
+               val |= u32_encode_bits(CFGCH_BW_V2_160M, RR_CFGCH_BW_V2);
+               break;
+       case RTW89_CHANNEL_WIDTH_320:
+               val |= u32_encode_bits(CFGCH_BW_V2_320M, RR_CFGCH_BW_V2);
+               break;
+       }
+
+       return val;
+}
+
 MODULE_FIRMWARE(RTW8922D_MODULE_FIRMWARE);
 MODULE_FIRMWARE(RTW8922DS_MODULE_FIRMWARE);
 MODULE_AUTHOR("Realtek Corporation");
index 147cf91d2cb043ae681874b4c231434bb7cade94..4e6a8e88a71e54158ee63a20790861c654cc7f80 100644 (file)
@@ -9,6 +9,12 @@
 #include "rtw8922d.h"
 #include "rtw8922d_rfk.h"
 
+static const struct rtw89_reg5_def rtw8922d_nctl_post_defs[] = {
+       RTW89_DECL_RFK_WM(0x20c7c, 0x00e00000, 0x1),
+};
+
+RTW89_DECLARE_RFK_TBL(rtw8922d_nctl_post_defs);
+
 static void rtw8922d_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
                                  enum rtw89_rf_path path, u8 phy_idx)
 {
@@ -239,6 +245,24 @@ set_rfk_reload:
        rtw8922d_chlk_reload(rtwdev);
 }
 
+static void rtw8922d_x4k_setting(struct rtw89_dev *rtwdev)
+{
+       u32 val;
+
+       val = rtw89_read_rf(rtwdev, RF_PATH_A, 0xB9, 0xF000);
+       rtw89_write_rf(rtwdev, RF_PATH_A, 0xB9, 0xF000, val);
+       val = rtw89_read_rf(rtwdev, RF_PATH_B, 0xB9, 0xF000);
+       rtw89_write_rf(rtwdev, RF_PATH_B, 0xB9, 0xF000, val);
+
+       rtw89_write_rf(rtwdev, RF_PATH_A, 0xC2, BIT(19), 0x1);
+       rtw89_write_rf(rtwdev, RF_PATH_B, 0xC2, BIT(19), 0x1);
+}
+
+void rtw8922d_rfk_hw_init(struct rtw89_dev *rtwdev)
+{
+       rtw8922d_x4k_setting(rtwdev);
+}
+
 void rtw8922d_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
 {
        bool mlo_1_1;
index 8a5f4b56b8ce3fbf4f6debdf7fdca30c1755201b..c5bbe0eb972ae5663cc3a183ec879a5ee4a61976 100644 (file)
@@ -7,10 +7,13 @@
 
 #include "core.h"
 
+extern const struct rtw89_rfk_tbl rtw8922d_nctl_post_defs_tbl;
+
 void rtw8922d_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx);
 void rtw8922d_set_channel_rf(struct rtw89_dev *rtwdev,
                             const struct rtw89_chan *chan,
                             enum rtw89_phy_idx phy_idx);
+void rtw8922d_rfk_hw_init(struct rtw89_dev *rtwdev);
 void rtw8922d_rfk_mlo_ctrl(struct rtw89_dev *rtwdev);
 void rtw8922d_pre_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
 void rtw8922d_post_set_channel_rf(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);