AN7581 SoC have more GPIOs. PCIE reset pins can be muxed to gpio,
so we have 50 GPIOs instead of 47.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Link: https://github.com/openwrt/openwrt/pull/24646
Signed-off-by: Robert Marko <robimarko@gmail.com>
};
&en7581_pinctrl {
- gpio-ranges = <&en7581_pinctrl 0 13 47>;
+ gpio-ranges = <&en7581_pinctrl 0 13 50>;
mdio_pins: mdio-pins {
mux {
};
&en7581_pinctrl {
- gpio-ranges = <&en7581_pinctrl 0 13 47>;
+ gpio-ranges = <&en7581_pinctrl 0 13 50>;
mdio_pins: mdio-pins {
mux {
};
&en7581_pinctrl {
- gpio-ranges = <&en7581_pinctrl 0 13 47>;
+ gpio-ranges = <&en7581_pinctrl 0 13 50>;
pcie1_rst_pins: pcie1-rst-pins {
conf {
};
&en7581_pinctrl {
- gpio-ranges = <&en7581_pinctrl 0 13 47>;
+ gpio-ranges = <&en7581_pinctrl 0 13 50>;
mdio_pins: mdio-pins {
mux {
};
&en7581_pinctrl {
- gpio-ranges = <&en7581_pinctrl 0 13 47>;
+ gpio-ranges = <&en7581_pinctrl 0 13 50>;
mdio_pins: mdio-pins {
mux {