RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548]

This patch fixes that AVL/VL reg incorrect fetch in VSETVL PASS.

C/C++ regression passed.

But gfortran didn't run yet. I am still finding a way to run it.

Will commit it when I pass the fortran regression.

	PR target/111548

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (earliest_pred_can_be_fused_p): Bugfix

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr111548.c: New test.

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index e0f61148ef330a8779f8fca7843a2f21d7743d83..7af33e7ea6f96bb171e7f54eab008b2b5c4c28e0 100644 (file)
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1514,7 +1514,6 @@ earliest_pred_can_be_fused_p (const bb_info *earliest_pred,
                              const vector_insn_info &earliest_info,
                              const vector_insn_info &expr, rtx *vlmax_vl)
 {
-  rtx vl = NULL_RTX;
   /* Backward VLMAX VL:
        bb 3:
         vsetivli zero, 1 ... -> vsetvli t1, zero
@@ -1526,10 +1525,9 @@ earliest_pred_can_be_fused_p (const bb_info *earliest_pred,
        We should forward "t1".  */
   if (!earliest_info.has_avl_reg () && expr.has_avl_reg ())
     {
-      rtx avl = expr.get_avl ();
+      rtx avl_or_vl_reg = expr.get_avl_or_vl_reg ();
+      gcc_assert (avl_or_vl_reg);
       const insn_info *last_insn = earliest_info.get_insn ();
-      if (vlmax_avl_p (avl))
-       vl = get_vl (expr.get_insn ()->rtl ());
       /* To fuse demand on earlest edge, we make sure AVL/VL
         didn't change from the consume insn to the predecessor
         of the edge.  */
@@ -1538,17 +1536,15 @@ earliest_pred_can_be_fused_p (const bb_info *earliest_pred,
           && after_or_same_p (i, last_insn);
           i = i->prev_nondebug_insn ())
        {
-         if (!vl && find_access (i->defs (), REGNO (avl)))
+         if (find_access (i->defs (), REGNO (avl_or_vl_reg)))
            return false;
-         if (vl && find_access (i->defs (), REGNO (vl)))
-           return false;
-         if (vl && find_access (i->uses (), REGNO (vl)))
+         if (find_access (i->uses (), REGNO (avl_or_vl_reg)))
            return false;
        }
+      if (vlmax_vl && vlmax_avl_p (expr.get_avl ()))
+       *vlmax_vl = avl_or_vl_reg;
     }
 
-  if (vlmax_vl)
-    *vlmax_vl = vl;
   return true;
 }
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111548.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111548.c
new file mode 100644 (file)
index 0000000..9bdf42d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111548.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -Wno-implicit-int -Wno-implicit-function-declaration -Wno-int-conversion" } */
+
+a, c, d; /* { dg-warning "data definition has no type or storage class" } */
+*b; /* { dg-warning "data definition has no type or storage class" } */
+h() {
+  int e;
+  i();
+  for (;;) {
+    unsigned f;
+    char *g;
+    f = a;
+    for (; f; f--) {
+      if (*g == '"')
+        e = !e;
+      *b = g++;
+    }
+    if (c)
+      break;
+    f = d;
+    for (; d;)
+      if (e)
+        b++;
+  }
+}