backport: tilegx.md (insn_v1mulu): Fix constraints on input operands.

	Backport from mainline:
	2013-03-27  Walter Lee  <walt@tilera.com>

	* config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on
	input operands.
	(insn_v1mulus): Ditto.
	(insn_v2muls): Ditto.

From-SVN: r197148

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 67486f464ee10e0c862ce18c360524dcc917b1ce..21f63415abac7b6099e403aec85fa504704d6069 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2013-03-27  Walter Lee  <walt@tilera.com>
+
+       Backport from mainline:
+       2013-03-27  Walter Lee  <walt@tilera.com>
+
+       * config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on
+       input operands.
+       (insn_v1mulus): Ditto.
+       (insn_v2muls): Ditto.
+
 2013-03-27  Walter Lee  <walt@tilera.com>
 
        Backport from mainline:

diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index ff845ae33f6e4d62e387cfdc54cd513cfde551cf..5a16fecb3b1c562de9624b3fbdc8737304ddbffb 100644 (file)
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -4508,8 +4508,8 @@
 
 (define_expand "insn_v1mulu"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_umult_lo_v8qi, V4HImode,
@@ -4538,8 +4538,8 @@
 
 (define_expand "insn_v1mulus"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_usmult_lo_v8qi, V4HImode,
@@ -4566,8 +4566,8 @@
 
 (define_expand "insn_v2muls"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_smult_lo_v4qi, V2SImode,