arm64: dts: renesas: r9a09g056: Add USB3 PHY/Host nodes

Add USB3 PHY/Host nodes to RZ/V2N ("R9A09G056") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251119110505.100253-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index c276cdc730bd0f2f300781a6566ebe73fb85b011..ac8b4a4f5fb7251120f34d5e59fb262d8489ed2a 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -694,6 +694,36 @@
                        status = "disabled";
                };
 
+               xhci: usb@15850000 {
+                       compatible = "renesas,r9a09g056-xhci", "renesas,r9a09g047-xhci";
+                       reg = <0 0x15850000 0 0x10000>;
+                       interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "all", "smi", "hse", "pme", "xhc";
+                       clocks = <&cpg CPG_MOD 0xaf>;
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0xaa>;
+                       phys = <&usb3_phy>, <&usb3_phy>;
+                       phy-names = "usb2-phy", "usb3-phy";
+                       status = "disabled";
+               };
+
+               usb3_phy: usb-phy@15870000 {
+                       compatible = "renesas,r9a09g056-usb3-phy", "renesas,r9a09g047-usb3-phy";
+                       reg = <0 0x15870000 0 0x10000>;
+                       clocks = <&cpg CPG_MOD 0xb0>,
+                                <&cpg CPG_CORE R9A09G056_USB3_0_CLKCORE>,
+                                <&cpg CPG_CORE R9A09G056_USB3_0_REF_ALT_CLK_P>;
+                       clock-names = "pclk", "core", "ref_alt_clk_p";
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0xaa>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
                sdhi0: mmc@15c00000  {
                        compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
                        reg = <0x0 0x15c00000 0 0x10000>;