drm/amd/display: Update HPO I/O When Handling Link Retrain Automation Request

[WHY]
Previous multi-display HPO fix moved where HPO I/O enable/disable is performed.
The codepath now taken to enable/disable HPO I/O is not used for compliance
test automation, meaning that if a compliance box being driven at a DP1 rate
requests retrain at UHBR, HPO I/O will remain off if it was previously off.

[HOW]
Explicitly update HPO I/O after allocating encoders for test request.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index b38340c690c6020796bde19c31ea8940ddf0522a..b6377efc6253109b1f8a632205ca0a832471a48a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -5303,3 +5303,16 @@ int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *o
        }
        return det_segments;
 }
+
+bool resource_is_hpo_acquired(struct dc_state *context)
+{
+       int i;
+
+       for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {
+               if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i]) {
+                       return true;
+               }
+       }
+
+       return false;
+}

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 217344ccf6440a064c0f0e414f30d2caf133612b..246fa300ee95c447c58ff33a14bda9dda9e1afb6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -2350,19 +2350,6 @@ static void dce110_setup_audio_dto(
        }
 }
 
-static bool dce110_is_hpo_enabled(struct dc_state *context)
-{
-       int i;
-
-       for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {
-               if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i]) {
-                       return true;
-               }
-       }
-
-       return false;
-}
-
 enum dc_status dce110_apply_ctx_to_hw(
                struct dc *dc,
                struct dc_state *context)
@@ -2371,8 +2358,8 @@ enum dc_status dce110_apply_ctx_to_hw(
        struct dc_bios *dcb = dc->ctx->dc_bios;
        enum dc_status status;
        int i;
-       bool was_hpo_enabled = dce110_is_hpo_enabled(dc->current_state);
-       bool is_hpo_enabled = dce110_is_hpo_enabled(context);
+       bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state);
+       bool is_hpo_acquired = resource_is_hpo_acquired(context);
 
        /* reset syncd pipes from disabled pipes */
        if (dc->config.use_pipe_ctx_sync_logic)
@@ -2415,8 +2402,8 @@ enum dc_status dce110_apply_ctx_to_hw(
 
        dce110_setup_audio_dto(dc, context);
 
-       if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_enabled != is_hpo_enabled) {
-               dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_enabled);
+       if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) {
+               dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired);
        }
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
index b57dd45611f234f05d560003bbc6c3a24f969a34..56f3c70d4b55486969c6c8f9ad35e0b5eefbb436 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
@@ -111,6 +111,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
        .optimize_pwr_state = dcn21_optimize_pwr_state,
        .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
        .update_visual_confirm_color = dcn10_update_visual_confirm_color,
+       .setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
 };
 
 static const struct hwseq_private_funcs dcn31_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
index fe5495a8e7a2b9f9566c1a8bc1d5811fb4e27659..68e6de6b5758d5d6037f5c8854291f20c5729513 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
@@ -114,6 +114,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = {
        .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
        .update_visual_confirm_color = dcn10_update_visual_confirm_color,
        .calculate_pix_rate_divider = dcn314_calculate_pix_rate_divider,
+       .setup_hpo_hw_control = dcn31_setup_hpo_hw_control,
 };
 
 static const struct hwseq_private_funcs dcn314_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index 5da3069fc1aba219e8dd9b7c468735d9d2a0f439..d00822e8daa52e3ad9f6fb69ebd09b213e5ca546 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -123,6 +123,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
        .set_long_vtotal = dcn35_set_long_vblank,
        .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,
        .program_outstanding_updates = dcn32_program_outstanding_updates,
+       .setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
 };
 
 static const struct hwseq_private_funcs dcn351_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 3268544898026b5ce715597daef6c768d68812f6..ac920562562336c579ff552aa04ab2b2be4de8d9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -461,6 +461,7 @@ struct hw_sequencer_funcs {
        void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max);
        void (*program_outstanding_updates)(struct dc *dc,
                        struct dc_state *context);
+       void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
 };
 
 void color_space_to_black_color(

diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 9cd80d3864c7b45679de64e8764f10fd203684ee..cd1157d225abe755d345b52e2b5fb67e88699636 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -644,4 +644,6 @@ void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuratio
  *Calculate total DET allocated for all pipes for a given OTG_MASTER pipe
  */
 int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master);
+
+bool resource_is_hpo_acquired(struct dc_state *context);
 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */

diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index df3781081da7aeb97d9b8c927cee6b3d398fe20e..ff8fe1a94965b9202b289ce3a96489da0e128da9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -67,6 +67,8 @@ static void dp_retrain_link_dp_test(struct dc_link *link,
 {
        struct pipe_ctx *pipes[MAX_PIPES];
        struct dc_state *state = link->dc->current_state;
+       bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state);
+       bool is_hpo_acquired;
        uint8_t count;
        int i;
 
@@ -83,6 +85,12 @@ static void dp_retrain_link_dp_test(struct dc_link *link,
                                pipes[i]);
        }
 
+       if (link->dc->hwss.setup_hpo_hw_control) {
+               is_hpo_acquired = resource_is_hpo_acquired(state);
+               if (was_hpo_acquired != is_hpo_acquired)
+                       link->dc->hwss.setup_hpo_hw_control(link->dc->hwseq, is_hpo_acquired);
+       }
+
        for (i = count-1; i >= 0; i--)
                link_set_dpms_on(state, pipes[i]);
 }