BUILD: makefile: stop opening sub-shells for each and every command

We're spending ~8% of the total build time calling a shell to display
"CC" using the "echo" command! We don't really need this, as make also
knows a "$(info ...)" command to print a message. However there's a catch,
this command trims leading spaces, so we need to use an invisible space
using "$ ". Furthermore, in GNU make 3.80 and older, $(info) doesn't show
anything, so we only do that for 3.81 and above, older versions continue
to use echo.

This measurably speeds up build time especially at -O0 that developers
use most of the time for quick checks.

diff --git a/Makefile b/Makefile
index c7d6ee98d9a59387b7fc0b64bda61dffb5f01ac4..c07ac2d080fa29a62f3dbc8cfece474535d3d3c4 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -813,10 +813,18 @@ cmd_CC = $(CC)
 cmd_LD = $(LD)
 cmd_AR = $(AR)
 else
+ifeq (3.81,$(firstword $(sort $(MAKE_VERSION) 3.81)))
+# 3.81 or above
+cmd_CC = $(info $   CC      $@) $(Q)$(CC)
+cmd_LD = $(info $   LD      $@) $(Q)$(LD)
+cmd_AR = $(info $   AR      $@) $(Q)$(AR)
+else
+# 3.80 or older
 cmd_CC = $(Q)echo "  CC      $@";$(CC)
 cmd_LD = $(Q)echo "  LD      $@";$(LD)
 cmd_AR = $(Q)echo "  AR      $@";$(AR)
 endif
+endif
 
 ifeq ($(TARGET),)
 all: