{
struct nand_device *nand = spinand_to_nand(spinand);
enum nand_ecc_engine_type engine_type = nand->ecc.ctx.conf.engine_type;
+ struct spi_controller *ctlr = spinand->spimem->spi->controller;
/* OOBs cannot be retrieved so external/on-host ECC engine won't work */
if (spinand->set_cont_read) {
*/
spinand_cont_read_enable(spinand, false);
- if (engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE ||
- engine_type == NAND_ECC_ENGINE_TYPE_NONE)
+ if ((engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE ||
+ engine_type == NAND_ECC_ENGINE_TYPE_NONE) &&
+ !spi_mem_controller_is_capable(ctlr, no_cs_assertion))
spinand->cont_read_possible = true;
}
}