coresight-etm4x: Conditionally access register TRCEXTINSELR

[ Upstream commit dcdc42f5dcf9b9197c51246c62966e2d54a033d8 ]

The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0.
To avoid invalid accesses, introduce a check on numextinsel
(derived from TRCIDR5[11:9]) before reading or writing to this register.

Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses")
Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250812-trcextinselr_issue-v2-1-e6eb121dfcf4@oss.qualcomm.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 1ad689db74da145ec12339e3e597dc86bcd2b72f..d89153d0517ecdceaebe1382d3bfc1b3ba8d8ad2 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -451,7 +451,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
                etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
                etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
        }
-       etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
+       if (drvdata->numextinsel)
+               etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
        for (i = 0; i < drvdata->nr_cntr; i++) {
                etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
                etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
@@ -1239,6 +1240,7 @@ static void etm4_init_arch_data(void *info)
        etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
        /* NUMEXTIN, bits[8:0] number of external inputs implemented */
        drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
+       drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
        /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
        drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
        /* ATBTRIG, bit[22] implementation can support ATB triggers? */
@@ -1671,7 +1673,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
                state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
                state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
        }
-       state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
+
+       if (drvdata->numextinsel)
+               state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
 
        for (i = 0; i < drvdata->nr_cntr; i++) {
                state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
@@ -1803,7 +1807,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
                etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
                etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
        }
-       etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
+       if (drvdata->numextinsel)
+               etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
 
        for (i = 0; i < drvdata->nr_cntr; i++) {
                etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 31754173091b925c82f55fd291412c19ca710286..b183d1d12f12993234b8cc4da78bd77c3a0addaa 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -162,6 +162,7 @@
 #define TRCIDR4_NUMVMIDC_MASK                  GENMASK(31, 28)
 
 #define TRCIDR5_NUMEXTIN_MASK                  GENMASK(8, 0)
+#define TRCIDR5_NUMEXTINSEL_MASK               GENMASK(11, 9)
 #define TRCIDR5_TRACEIDSIZE_MASK               GENMASK(21, 16)
 #define TRCIDR5_ATBTRIG                                BIT(22)
 #define TRCIDR5_LPOVERRIDE                     BIT(23)
@@ -995,6 +996,7 @@ struct etmv4_drvdata {
        u8                              nr_cntr;
        u8                              nr_ext_inp;
        u8                              numcidc;
+       u8                              numextinsel;
        u8                              numvmidc;
        u8                              nrseqstate;
        u8                              nr_event;