clk: mediatek: fix fixed clock parents

Add a flags field to struct mtk_fixed_clk to allow properly resolving
the parent clock. All chip-specific clocks are updated to populate this
field correctly.

The parent is currently only used for printing debug information, so
there are no functional bugs being fixed.

Signed-off-by: David Lechner <dlechner@baylibre.com>

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 9621d5efe11a510e89e3426c35cc14c7279ffd52..782eb14e9c507df2e94ba910e69f9c4c10573351 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -85,6 +85,9 @@ static const struct mtk_gate apmixed_cgs[] = {
 };
 
 /* topckgen */
+#define FIXED_CLK0(_id, _rate)                                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
 #define FACTOR0(_id, _parent, _mult, _div)                     \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -95,16 +98,16 @@ static const struct mtk_gate apmixed_cgs[] = {
        FACTOR(_id, _parent, _mult, _div, 0)
 
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
-       FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
-       FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
-       FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
-       FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
-       FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
-       FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
-       FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
-       FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
-       FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
+       FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000),
+       FIXED_CLK0(CLK_TOP_TO_U2_PHY_1P, 31250000),
+       FIXED_CLK0(CLK_TOP_PCIE0_PIPE_EN, 125000000),
+       FIXED_CLK0(CLK_TOP_PCIE1_PIPE_EN, 125000000),
+       FIXED_CLK0(CLK_TOP_SSUSB_TX250M, 250000000),
+       FIXED_CLK0(CLK_TOP_SSUSB_EQ_RX250M, 250000000),
+       FIXED_CLK0(CLK_TOP_SSUSB_CDR_REF, 33333333),
+       FIXED_CLK0(CLK_TOP_SSUSB_CDR_FB, 50000000),
+       FIXED_CLK0(CLK_TOP_SATA_ASIC, 50000000),
+       FIXED_CLK0(CLK_TOP_SATA_RBC, 50000000),
 };
 
 static const struct mtk_fixed_factor top_fixed_divs[] = {

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 3509ea67e7dd4999d760057db80fc4f4e4a7d193..071c4cf8a843d50f4d7b040a63d3e37c01c16878 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -259,6 +259,9 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = {
        [CLK_TOP_AUD_I2S6_MCLK]                 = 158,
 };
 
+#define FIXED_CLK0(_id, _rate)                                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
 #define FACTOR0(_id, _parent, _mult, _div)                     \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -269,21 +272,21 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = {
        FACTOR(_id, _parent, _mult, _div, 0)
 
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
-       FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
-       FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
-       FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
-       FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
-       FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
-       FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
-       FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
-       FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
-       FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
-       FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
-       FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),
-       FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),
-       FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),
-       FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),
+       FIXED_CLK0(CLK_TOP_DPI, 108 * MHZ),
+       FIXED_CLK0(CLK_TOP_DMPLL, 400 * MHZ),
+       FIXED_CLK0(CLK_TOP_VENCPLL, 295.75 * MHZ),
+       FIXED_CLK0(CLK_TOP_HDMI_0_PIX340M, 340 * MHZ),
+       FIXED_CLK0(CLK_TOP_HDMI_0_DEEP340M, 340 * MHZ),
+       FIXED_CLK0(CLK_TOP_HDMI_0_PLL340M, 340 * MHZ),
+       FIXED_CLK0(CLK_TOP_HADDS2_FB, 27 * MHZ),
+       FIXED_CLK0(CLK_TOP_WBG_DIG_416M, 416 * MHZ),
+       FIXED_CLK0(CLK_TOP_DSI0_LNTC_DSI, 143 * MHZ),
+       FIXED_CLK0(CLK_TOP_HDMI_SCL_RX, 27 * MHZ),
+       FIXED_CLK0(CLK_TOP_32K_EXTERNAL, 32000),
+       FIXED_CLK0(CLK_TOP_HDMITX_CLKDIG_CTS, 300 * MHZ),
+       FIXED_CLK0(CLK_TOP_AUD_EXT1, 0),
+       FIXED_CLK0(CLK_TOP_AUD_EXT2, 0),
+       FIXED_CLK0(CLK_TOP_NFI1X_PAD, 0),
 };
 
 static const struct mtk_fixed_factor top_fixed_divs[] = {

diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 5bbac309e9d13bfede7b0d0ad0c53ff166f42e10..582394f594bc01a5d6e6c3e93646a060f6bcea82 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -61,6 +61,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
 };
 
 /* topckgen */
+#define FIXED_CLK0(_id, _rate)                                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
 #define FACTOR0(_id, _parent, _mult, _div)                     \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -71,16 +74,16 @@ static const struct mtk_pll_data apmixed_plls[] = {
        FACTOR(_id, _parent, _mult, _div, 0)
 
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
-       FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
-       FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
-       FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
-       FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
-       FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
-       FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
-       FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
-       FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
-       FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
+       FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000),
+       FIXED_CLK0(CLK_TOP_TO_U2_PHY_1P, 31250000),
+       FIXED_CLK0(CLK_TOP_PCIE0_PIPE_EN, 125000000),
+       FIXED_CLK0(CLK_TOP_PCIE1_PIPE_EN, 125000000),
+       FIXED_CLK0(CLK_TOP_SSUSB_TX250M, 250000000),
+       FIXED_CLK0(CLK_TOP_SSUSB_EQ_RX250M, 250000000),
+       FIXED_CLK0(CLK_TOP_SSUSB_CDR_REF, 33333333),
+       FIXED_CLK0(CLK_TOP_SSUSB_CDR_FB, 50000000),
+       FIXED_CLK0(CLK_TOP_SATA_ASIC, 50000000),
+       FIXED_CLK0(CLK_TOP_SATA_RBC, 50000000),
 };
 
 static const struct mtk_fixed_factor top_fixed_divs[] = {

diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 3f96d25db047d15fd315fbb56dfac2a2b1e8f38e..09ed4d8a97f88c071630f4e9b32bd63abc076ec3 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -18,6 +18,9 @@
 #define MT7981_CLK_PDN 0x250
 #define MT7981_CLK_PDN_EN_WRITE BIT(31)
 
+#define FIXED_CLK0(_id, _rate)                                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
 #define PLL_FACTOR(_id, _name, _parent, _mult, _div)                           \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -29,19 +32,19 @@
 
 /* FIXED PLLS */
 static const struct mtk_fixed_clk fixed_pll_clks[] = {
-       FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
-       FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
-       FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),
-       FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
-       FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
-       FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
-       FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
-       FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
+       FIXED_CLK0(CLK_APMIXED_ARMPLL, 1300000000),
+       FIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000),
+       FIXED_CLK0(CLK_APMIXED_MMPLL, 720000000),
+       FIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000),
+       FIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 208000000),
+       FIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000),
+       FIXED_CLK0(CLK_APMIXED_MPLL, 416000000),
+       FIXED_CLK0(CLK_APMIXED_APLL2, 196608000),
 };
 
 /* TOPCKGEN FIXED CLK */
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
+       FIXED_CLK0(CLK_TOP_CB_CKSQ_40M, 40000000),
 };
 
 /* TOPCKGEN FIXED DIV */

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index a8f39a3beb6ca677c1578055ab137e3de52ac53a..79efbf43bc43deb3d2ddc4d0bf9861a828e0f39e 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -23,6 +23,9 @@
 #define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
 #define VOID_PARENT PARENT(-1, 0)
 
+#define FIXED_CLK0(_id, _rate)                                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
 #define PLL_FACTOR(_id, _name, _parent, _mult, _div)                           \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -34,19 +37,19 @@
 
 /* FIXED PLLS */
 static const struct mtk_fixed_clk fixed_pll_clks[] = {
-       FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
-       FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
-       FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
-       FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
-       FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
-       FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
-       FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
-       FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
+       FIXED_CLK0(CLK_APMIXED_ARMPLL, 2000000000),
+       FIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000),
+       FIXED_CLK0(CLK_APMIXED_MMPLL, 1440000000),
+       FIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000),
+       FIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 760000000),
+       FIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000),
+       FIXED_CLK0(CLK_APMIXED_MPLL, 416000000),
+       FIXED_CLK0(CLK_APMIXED_APLL2, 196608000),
 };
 
 /* TOPCKGEN FIXED CLK */
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
+       FIXED_CLK0(CLK_TOP_XTAL, 40000000),
 };
 
 /* TOPCKGEN FIXED DIV */

diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c
index 818f45ef6bbfd5fb8b39a3fb9c26922ce5ae54e8..959b1c9cff69912d4fc52446afe6df23109bdcc5 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7987.c
+++ b/drivers/clk/mediatek/clk-mt7987.c
@@ -19,6 +19,9 @@
 #define MT7987_CLK_PDN         0x250
 #define MT7987_CLK_PDN_EN_WRITE        BIT(31)
 
+#define FIXED_CLK0(_id, _rate)                                                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
 #define XTAL_FACTOR(_id, _name, _parent, _mult, _div)                          \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
 
@@ -33,14 +36,14 @@
 
 /* FIXED PLLS */
 static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
-       FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
-       FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
-       FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
-       FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
-       FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
-       FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
-       FIXED_CLK(CLK_APMIXED_ARM_LL, CLK_XTAL, 2000000000),
-       FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 384000000),
+       FIXED_CLK0(CLK_APMIXED_MPLL, 416000000),
+       FIXED_CLK0(CLK_APMIXED_APLL2, 196608000),
+       FIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000),
+       FIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000),
+       FIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 208000000),
+       FIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000),
+       FIXED_CLK0(CLK_APMIXED_ARM_LL, 2000000000),
+       FIXED_CLK0(CLK_APMIXED_MSDCPLL, 384000000),
 };
 
 static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {

diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 6da7c62c585cb0c8e011d7698322bb41527e531e..cd8726852d7c729a8e3cefbc61148a44dc3df7c5 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -21,6 +21,9 @@
 #define MT7988_ETHDMA_RST_CTRL_OFS     0x34
 #define MT7988_ETHWARP_RST_CTRL_OFS    0x8
 
+#define FIXED_CLK0(_id, _rate)                                                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
 #define XTAL_FACTOR(_id, _name, _parent, _mult, _div)                          \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
 
@@ -35,23 +38,23 @@
 
 /* FIXED PLLS */
 static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
-       FIXED_CLK(CLK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
-       FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
-       FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),
-       FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
-       FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
-       FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
-       FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
-       FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
-       FIXED_CLK(CLK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
-       FIXED_CLK(CLK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
-       FIXED_CLK(CLK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
-       FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
+       FIXED_CLK0(CLK_APMIXED_NETSYSPLL, 850000000),
+       FIXED_CLK0(CLK_APMIXED_MPLL, 416000000),
+       FIXED_CLK0(CLK_APMIXED_MMPLL, 720000000),
+       FIXED_CLK0(CLK_APMIXED_APLL2, 196608000),
+       FIXED_CLK0(CLK_APMIXED_NET1PLL, 2500000000),
+       FIXED_CLK0(CLK_APMIXED_NET2PLL, 800000000),
+       FIXED_CLK0(CLK_APMIXED_WEDMCUPLL, 208000000),
+       FIXED_CLK0(CLK_APMIXED_SGMPLL, 325000000),
+       FIXED_CLK0(CLK_APMIXED_ARM_B, 1500000000),
+       FIXED_CLK0(CLK_APMIXED_CCIPLL2_B, 960000000),
+       FIXED_CLK0(CLK_APMIXED_USXGMIIPLL, 644533000),
+       FIXED_CLK0(CLK_APMIXED_MSDCPLL, 400000000),
 };
 
 /* TOPCKGEN FIXED CLK */
 static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
+       FIXED_CLK0(CLK_TOP_XTAL, 40000000),
 };
 
 /* TOPCKGEN FIXED DIV */

diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 5a353e82f3f5a50e3ccf90348571100bc015a5af..9d9d00622dbdc565b6af5056470c8cd5617016df 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -67,10 +67,16 @@ static const struct mtk_pll_data apmixed_plls[] = {
            0, 0, 32, 8, 0x02B4, 1, 0x02B8, 0),
 };
 
+#define FIXED_CLK0(_id, _rate)                                         \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
+#define FIXED_CLK1(_id, _rate)                                         \
+       FIXED_CLK(_id, CLK_TOP_UNIVPLL, CLK_PARENT_TOPCKGEN, _rate)
+
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000),
-       FIXED_CLK(CLK_TOP_ULPOSC, CLK_XTAL, 250000),
-       FIXED_CLK(CLK_TOP_UNIVP_192M, CLK_TOP_UNIVPLL, 192000000),
+       FIXED_CLK0(CLK_TOP_CLK26M, 26000000),
+       FIXED_CLK0(CLK_TOP_ULPOSC, 250000),
+       FIXED_CLK1(CLK_TOP_UNIVP_192M, 192000000),
 };
 
 static const struct mtk_fixed_factor top_fixed_divs[] = {

diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index d967a915fac6f5d6a8d6fb7aec859ea3a04e5c5d..64aeaa5949f679330f01987063387c52bb75e6cd 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -88,15 +88,18 @@ static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = {
        .num_plls = ARRAY_SIZE(apmixed_plls),
 };
 
+#define FIXED_CLK0(_id, _rate)                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_ULPOSC1, CLK_XTAL, 260000000),
-       FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, CLK_XTAL, 49152000),
-       FIXED_CLK(CLK_TOP_PAD_FPC, CLK_XTAL, 50000000),
-       FIXED_CLK(CLK_TOP_466M_FMEM, CLK_XTAL, 533000000),
-       FIXED_CLK(CLK_TOP_PEXTP_PIPE, CLK_XTAL, 250000000),
-       FIXED_CLK(CLK_TOP_DSI_PHY, CLK_XTAL, 500000000),
-       FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 260000000),
-       FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+       FIXED_CLK0(CLK_TOP_ULPOSC1, 260000000),
+       FIXED_CLK0(CLK_TOP_MPHONE_SLAVE_BCK, 49152000),
+       FIXED_CLK0(CLK_TOP_PAD_FPC, 50000000),
+       FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000),
+       FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000),
+       FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000),
+       FIXED_CLK0(CLK_TOP_CLK26M, 260000000),
+       FIXED_CLK0(CLK_TOP_CLK32K, 32000),
 };
 
 #define FACTOR0(_id, _parent, _mult, _div)     \

diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index 02d30ab12d8e14c408999f8766017888c722edc6..13f63d04ad0978a8120cb15c0b3043379cffeef0 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -68,12 +68,18 @@ static const struct mtk_pll_data apmixed_plls[] = {
 };
 
 /* topckgen */
+#define FIXED_CLK0(_id, _rate)                                         \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
+#define FIXED_CLK1(_id, _rate)                                         \
+       FIXED_CLK(_id, CLK_TOP_CLK26M, CLK_PARENT_TOPCKGEN, _rate)
+
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 0),
-       FIXED_CLK(CLK_TOP_I2S0_BCK, CLK_XTAL, 26000000),
-       FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, CLK_TOP_CLK26M, 75000000),
-       FIXED_CLK(CLK_TOP_VPLL_DPIX, CLK_TOP_CLK26M, 75000000),
-       FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, CLK_TOP_CLK26M, 52500000),
+       FIXED_CLK0(CLK_TOP_CLK_NULL, 0),
+       FIXED_CLK0(CLK_TOP_I2S0_BCK, 26000000),
+       FIXED_CLK1(CLK_TOP_DSI0_LNTC_DSICK, 75000000),
+       FIXED_CLK1(CLK_TOP_VPLL_DPIX, 75000000),
+       FIXED_CLK1(CLK_TOP_LVDSTX_CLKDIG_CTS, 52500000),
 };
 
 #define PLL_FACTOR(_id, _name, _parent, _mult, _div)                   \

diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index bad8c62601d773cacded592322abdae8a8a9273c..e6ced91fd06f76235f4bc52500ba4a0cfdf4c086 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -59,6 +59,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
 };
 
 /* topckgen */
+#define FIXED_CLK0(_id, _rate)                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
 #define FACTOR0(_id, _parent, _mult, _div)     \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -69,8 +72,8 @@ static const struct mtk_pll_data apmixed_plls[] = {
        FACTOR(_id, _parent, _mult, _div, 0)
 
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
-       FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+       FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000),
+       FIXED_CLK0(CLK_TOP_CLK32K, 32000),
 };
 
 static const struct mtk_fixed_factor top_fixed_divs[] = {

diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index a84a5f360f5f1033c0de990cf73df412f82a1d84..4985ba3e5ce3e3e8c64b20b8890d8ae4363103b4 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -49,6 +49,12 @@ static const struct mtk_pll_data apmixed_plls[] = {
 };
 
 /* topckgen */
+#define FIXED_CLK0(_id, _rate)                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
+#define FIXED_CLK1(_id, _parent, _rate)                \
+       FIXED_CLK(_id, _parent, CLK_PARENT_TOPCKGEN, _rate)
+
 #define FACTOR0(_id, _parent, _mult, _div)     \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -59,9 +65,9 @@ static const struct mtk_pll_data apmixed_plls[] = {
        FACTOR(_id, _parent, _mult, _div, 0)
 
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
-       FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
-       FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
+       FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000),
+       FIXED_CLK1(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
+       FIXED_CLK1(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
 };
 
 static const struct mtk_fixed_factor top_fixed_divs[] = {

diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 43a06217d338c3b27c0ebef300b86a9a6e1530c1..2fc492e717004ed5524b1725029169ae6fa2d9ee 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -51,6 +51,12 @@ static const struct mtk_pll_data apmixed_plls[] = {
 };
 
 /* topckgen */
+#define FIXED_CLK0(_id, _rate)                 \
+       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+
+#define FIXED_CLK1(_id, _rate)                 \
+       FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate)
+
 #define FACTOR0(_id, _parent, _mult, _div)     \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
 
@@ -61,10 +67,10 @@ static const struct mtk_pll_data apmixed_plls[] = {
        FACTOR(_id, _parent, _mult, _div, 0)
 
 static const struct mtk_fixed_clk top_fixed_clks[] = {
-       FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
-       FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000),
-       FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000),
-       FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+       FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000),
+       FIXED_CLK1(CLK_TOP_FQ_TRNG_OUT0, 500000000),
+       FIXED_CLK1(CLK_TOP_FQ_TRNG_OUT1, 500000000),
+       FIXED_CLK0(CLK_TOP_CLK32K, 32000),
 };
 
 static const struct mtk_fixed_factor top_fixed_divs[] = {

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 6ba2fabfd08dc90f669ef2e47c4f42ef69d28d79..e370d304c032dddd7f8458e30bc189af9c200686 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -798,8 +798,7 @@ static void mtk_topckgen_dump(struct udevice *dev)
                printf("[FCLK%u] DT: %u", i, fclk->id);
                mtk_clk_print_mapped_id(fclk->id, i, tree->id_offs_map);
                mtk_clk_print_rate(dev, i);
-               /* FIXME: fclk needs flags to fully determine parent. */
-               mtk_clk_print_single_parent(fclk->parent, 0);
+               mtk_clk_print_single_parent(fclk->parent, fclk->flags);
                printf("\n");
        }
 

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 068240b123ef0eb873c7cbc7cea624d926c9c2d2..e618e982e8b903f2856bbd180b4336e1343dd9c9 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -73,12 +73,14 @@ struct mtk_pll_data {
 struct mtk_fixed_clk {
        const int id;
        const int parent;
+       const int flags;
        unsigned long rate;
 };
 
-#define FIXED_CLK(_id, _parent, _rate) {               \
+#define FIXED_CLK(_id, _parent, _flags, _rate) {       \
                .id = _id,                              \
                .parent = _parent,                      \
+               .flags = _flags,                        \
                .rate = _rate,                          \
        }