irqchip/ocelot: Fix trigger register address

Controllers, supported by this driver, have two sets of registers:

 * (main) interrupt registers control peripheral interrupt sources.

 * device interrupt registers configure per-device (network interface)
   interrupts and act as an extra stage before the main interrupt
   registers.

In the driver unmask code, device trigger registers are used in the mask
calculation of the main interrupt sticky register, mixing two kinds of
registers.

Use the main interrupt trigger register instead.

Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240925184416.54204-2-matsievskiysv@gmail.com

diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index 4d0c3532dbe735239d971aece0444baa9eba55e8..c19ab379e8c5ea85f387cb0ce754c4c057fdaee7 100644 (file)
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -37,7 +37,7 @@ static struct chip_props ocelot_props = {
        .reg_off_ena_clr        = 0x1c,
        .reg_off_ena_set        = 0x20,
        .reg_off_ident          = 0x38,
-       .reg_off_trigger        = 0x5c,
+       .reg_off_trigger        = 0x4,
        .n_irq                  = 24,
 };
 
@@ -70,7 +70,7 @@ static struct chip_props jaguar2_props = {
        .reg_off_ena_clr        = 0x1c,
        .reg_off_ena_set        = 0x20,
        .reg_off_ident          = 0x38,
-       .reg_off_trigger        = 0x5c,
+       .reg_off_trigger        = 0x4,
        .n_irq                  = 29,
 };