/**
* amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
*
+ * @adev: amdgpu device pointer
* @mask: array in which the per-shader array disable masks will be stored
* @max_se: number of SEs
* @max_sh: number of SHs
* The bitmask of CUs to be disabled in the shader array determined by se and
* sh is stored in mask[se * max_sh + sh].
*/
-void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se, unsigned int max_sh)
+void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask,
+ unsigned int max_se, unsigned int max_sh)
{
unsigned int se, sh, cu;
const char *p;
return (u32)((1ULL << bit_width) - 1);
}
-void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
- unsigned max_sh);
+void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask,
+ unsigned int max_se, unsigned int max_sh);
int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id);
if (!adev || !cu_info)
return -EINVAL;
- amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
+ amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
if (!adev || !cu_info)
return -EINVAL;
- amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
+ amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
if (!adev || !cu_info)
return -EINVAL;
- amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
+ amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
return -EINVAL;
}
- amdgpu_gfx_parse_disable_cu(disable_masks,
+ amdgpu_gfx_parse_disable_cu(adev, disable_masks,
adev->gfx.config.max_shader_engines,
adev->gfx.config.max_sh_per_se);
memset(cu_info, 0, sizeof(*cu_info));
- amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
+ amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
memset(cu_info, 0, sizeof(*cu_info));
- amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
+ amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
else
ao_cu_num = adev->gfx.config.max_cu_per_sh;
- amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
+ amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
adev->gfx.config.max_sh_per_se > 16)
return -EINVAL;
- amdgpu_gfx_parse_disable_cu(disable_masks,
+ amdgpu_gfx_parse_disable_cu(adev, disable_masks,
adev->gfx.config.max_shader_engines,
adev->gfx.config.max_sh_per_se);
adev->gfx.config.max_sh_per_se > 16)
return -EINVAL;
- amdgpu_gfx_parse_disable_cu(disable_masks,
+ amdgpu_gfx_parse_disable_cu(adev, disable_masks,
adev->gfx.config.max_shader_engines,
adev->gfx.config.max_sh_per_se);