arm64: dts: qcom: sm6350: Fix GPU frequencies missing on some speedbins

[ Upstream commit 600c499f8f5297c2c91e8146a8217f299e445ef6 ]

Make sure the GPU frequencies are marked as supported for the respective
speedbins according to downstream msm-4.19 kernel:

* 850 MHz: Speedbins 0 + 180
* 800 MHz: Speedbins 0 + 180 + 169
* 650 MHz: Speedbins 0 + 180 + 169 + 138
* 565 MHz: Speedbins 0 + 180 + 169 + 138 + 120
* 430 MHz: Speedbins 0 + 180 + 169 + 138 + 120
* 355 MHz: Speedbins 0 + 180 + 169 + 138 + 120
* 253 MHz: Speedbins 0 + 180 + 169 + 138 + 120

Fixes: bd9b76750280 ("arm64: dts: qcom: sm6350: Add GPU nodes")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20241002-sm6350-gpu-speedbin-fix-v1-1-8a5d90c5097d@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 7986ddb30f6e8ce6ceeb0f90772b0243aed6bffe..4f8477de7e1b1e8ea5c4d193e16dcdadc20eb4ff 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1376,43 +1376,43 @@
                                opp-850000000 {
                                        opp-hz = /bits/ 64 <850000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
-                                       opp-supported-hw = <0x02>;
+                                       opp-supported-hw = <0x03>;
                                };
 
                                opp-800000000 {
                                        opp-hz = /bits/ 64 <800000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
-                                       opp-supported-hw = <0x04>;
+                                       opp-supported-hw = <0x07>;
                                };
 
                                opp-650000000 {
                                        opp-hz = /bits/ 64 <650000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
-                                       opp-supported-hw = <0x08>;
+                                       opp-supported-hw = <0x0f>;
                                };
 
                                opp-565000000 {
                                        opp-hz = /bits/ 64 <565000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
-                                       opp-supported-hw = <0x10>;
+                                       opp-supported-hw = <0x1f>;
                                };
 
                                opp-430000000 {
                                        opp-hz = /bits/ 64 <430000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
-                                       opp-supported-hw = <0xff>;
+                                       opp-supported-hw = <0x1f>;
                                };
 
                                opp-355000000 {
                                        opp-hz = /bits/ 64 <355000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
-                                       opp-supported-hw = <0xff>;
+                                       opp-supported-hw = <0x1f>;
                                };
 
                                opp-253000000 {
                                        opp-hz = /bits/ 64 <253000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
-                                       opp-supported-hw = <0xff>;
+                                       opp-supported-hw = <0x1f>;
                                };
                        };
                };