riscv: Fix RV32 libthread_db THREAD_SELF register layout

The RISC-V libthread_db THREAD_SELF descriptor currently assumes 64-bit
general-register slots:

  REGISTER (64, 64, 4 * 8, ...)

That is correct for RV64, where tp/x4 is at byte offset 4 * 8 in the
general register set.  On RV32, general-register slots are 32-bit wide,
so tp/x4 is at byte offset 4 * 4.

Using the RV64 layout on RV32 makes libthread_db read the wrong thread
pointer value and prevents GDB from enabling pthread-aware thread
debugging.

Use a helper macro to pass the RISC-V register size into the
DB_THREAD_SELF definition.

Signed-off-by: Shengwen Cheng <shengwen1997.tw@gmail.com>
Reviewed-by: Peter Bergner <bergner@tenstorrent.com>

diff --git a/sysdeps/riscv/nptl/tls.h b/sysdeps/riscv/nptl/tls.h
index b2e0f3c249dab6a699f2fea858e3ea3d12a4a2d5..1e46e93669625b304bde5092aeac1c83c1e2afdf 100644 (file)
--- a/sysdeps/riscv/nptl/tls.h
+++ b/sysdeps/riscv/nptl/tls.h
@@ -96,8 +96,9 @@ typedef struct
 
 /* Informs libthread_db that the thread pointer is register 4, which is used
  * to know how to do THREAD_SELF.  */
-# define DB_THREAD_SELF \
-  REGISTER (64, 64, 4 * 8, - TLS_TCB_OFFSET - TLS_PRE_TCB_SIZE)
+# define DB_THREAD_SELF_REGISTER(bits) \
+  REGISTER (bits, bits, 4 * bits / 8, - TLS_TCB_OFFSET - TLS_PRE_TCB_SIZE)
+# define DB_THREAD_SELF DB_THREAD_SELF_REGISTER (__riscv_xlen)
 
 /* Access to data in the thread descriptor is easy.  */
 # include <tcb-access.h>