arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
agilex5 device tree. This update configures the SPI controller to use a
4-bit bus width for both transmission and reception, potentially improving
SPI throughput and matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index e9776e1cdc9a004d7f806a667b29fc6fa51ab0e4..262bb3e8e5c7248a2f7ad93678025d9a2478d9a2 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -77,6 +77,8 @@
                cdns,tsd2d-ns = <50>;
                cdns,tchsh-ns = <4>;
                cdns,tslch-ns = <4>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
 
                partitions {
                        compatible = "fixed-partitions";