}
static int loongarch_eiointc_readb(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
- gpa_t addr, int len, void *val)
+ gpa_t addr, void *val)
{
int index, ret = 0;
u8 data = 0;
}
static int loongarch_eiointc_readw(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
- gpa_t addr, int len, void *val)
+ gpa_t addr, void *val)
{
int index, ret = 0;
u16 data = 0;
}
static int loongarch_eiointc_readl(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
- gpa_t addr, int len, void *val)
+ gpa_t addr, void *val)
{
int index, ret = 0;
u32 data = 0;
}
static int loongarch_eiointc_readq(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
- gpa_t addr, int len, void *val)
+ gpa_t addr, void *val)
{
int index, ret = 0;
u64 data = 0;
spin_lock_irqsave(&eiointc->lock, flags);
switch (len) {
case 1:
- ret = loongarch_eiointc_readb(vcpu, eiointc, addr, len, val);
+ ret = loongarch_eiointc_readb(vcpu, eiointc, addr, val);
break;
case 2:
- ret = loongarch_eiointc_readw(vcpu, eiointc, addr, len, val);
+ ret = loongarch_eiointc_readw(vcpu, eiointc, addr, val);
break;
case 4:
- ret = loongarch_eiointc_readl(vcpu, eiointc, addr, len, val);
+ ret = loongarch_eiointc_readl(vcpu, eiointc, addr, val);
break;
case 8:
- ret = loongarch_eiointc_readq(vcpu, eiointc, addr, len, val);
+ ret = loongarch_eiointc_readq(vcpu, eiointc, addr, val);
break;
default:
WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n",
static int loongarch_eiointc_writeb(struct kvm_vcpu *vcpu,
struct loongarch_eiointc *s,
- gpa_t addr, int len, const void *val)
+ gpa_t addr, const void *val)
{
int index, irq, bits, ret = 0;
u8 cpu;
static int loongarch_eiointc_writew(struct kvm_vcpu *vcpu,
struct loongarch_eiointc *s,
- gpa_t addr, int len, const void *val)
+ gpa_t addr, const void *val)
{
int i, index, irq, bits, ret = 0;
u8 cpu;
static int loongarch_eiointc_writel(struct kvm_vcpu *vcpu,
struct loongarch_eiointc *s,
- gpa_t addr, int len, const void *val)
+ gpa_t addr, const void *val)
{
int i, index, irq, bits, ret = 0;
u8 cpu;
static int loongarch_eiointc_writeq(struct kvm_vcpu *vcpu,
struct loongarch_eiointc *s,
- gpa_t addr, int len, const void *val)
+ gpa_t addr, const void *val)
{
int i, index, irq, bits, ret = 0;
u8 cpu;
spin_lock_irqsave(&eiointc->lock, flags);
switch (len) {
case 1:
- ret = loongarch_eiointc_writeb(vcpu, eiointc, addr, len, val);
+ ret = loongarch_eiointc_writeb(vcpu, eiointc, addr, val);
break;
case 2:
- ret = loongarch_eiointc_writew(vcpu, eiointc, addr, len, val);
+ ret = loongarch_eiointc_writew(vcpu, eiointc, addr, val);
break;
case 4:
- ret = loongarch_eiointc_writel(vcpu, eiointc, addr, len, val);
+ ret = loongarch_eiointc_writel(vcpu, eiointc, addr, val);
break;
case 8:
- ret = loongarch_eiointc_writeq(vcpu, eiointc, addr, len, val);
+ ret = loongarch_eiointc_writeq(vcpu, eiointc, addr, val);
break;
default:
WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n",