drm/i915/mchbar: Use intel_mchbar_read*() instead of intel_uncore_read*()

Replace all the naked intel_uncore_read*() accesses to MCHBAR
registers with the dedicated intel_mchbar_read*().

v2: Rebase due to the intel_mchbar_read64_2x32() rename

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260331154259.24600-7-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index c39d56e2ea262510830fc49847ffad0b891835eb..3dbfb850fe1d37a63338fa19953b4a7cd6012008 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -19,6 +19,7 @@
 #include "intel_display_utils.h"
 #include "intel_dram.h"
 #include "intel_fb.h"
+#include "intel_mchbar.h"
 #include "intel_mchbar_regs.h"
 #include "intel_wm.h"
 #include "skl_watermark.h"
@@ -2742,12 +2743,11 @@ static void ilk_compute_wm_level(struct intel_display *display,
 
 static void hsw_read_wm_latency(struct intel_display *display, u16 wm[])
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u64 sskpd;
 
        display->wm.num_levels = 5;
 
-       sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
+       sskpd = intel_mchbar_read64_2x32(display, MCH_SSKPD);
 
        wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
        if (wm[0] == 0)
@@ -2760,12 +2760,11 @@ static void hsw_read_wm_latency(struct intel_display *display, u16 wm[])
 
 static void snb_read_wm_latency(struct intel_display *display, u16 wm[])
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u32 sskpd;
 
        display->wm.num_levels = 4;
 
-       sskpd = intel_uncore_read(uncore, MCH_SSKPD);
+       sskpd = intel_mchbar_read(display, MCH_SSKPD);
 
        wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
        wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
@@ -2775,12 +2774,11 @@ static void snb_read_wm_latency(struct intel_display *display, u16 wm[])
 
 static void ilk_read_wm_latency(struct intel_display *display, u16 wm[])
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u32 mltr;
 
        display->wm.num_levels = 3;
 
-       mltr = intel_uncore_read(uncore, MLTR_ILK);
+       mltr = intel_mchbar_read(display, MLTR_ILK);
 
        /* ILK primary LP0 latency is 700 ns */
        wm[0] = 7;

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 18b80147ddc7394a080d371258687e8e431d3625..e6c8fd6302947eb03b5406ca5e045810537ada49 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -15,9 +15,9 @@
 #include "intel_display_types.h"
 #include "intel_display_utils.h"
 #include "intel_dram.h"
+#include "intel_mchbar.h"
 #include "intel_mchbar_regs.h"
 #include "intel_parent.h"
-#include "intel_uncore.h"
 #include "skl_watermark.h"
 
 struct intel_bw_state {
@@ -75,11 +75,10 @@ static int dg1_mchbar_read_qgv_point_info(struct intel_display *display,
                                          struct intel_qgv_point *sp,
                                          int point)
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u32 dclk_ratio, dclk_reference;
        u32 val;
 
-       val = intel_uncore_read(uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
+       val = intel_mchbar_read(display, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
        dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
        if (val & DG1_QCLK_REFERENCE)
                dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
@@ -87,18 +86,18 @@ static int dg1_mchbar_read_qgv_point_info(struct intel_display *display,
                dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
        sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);
 
-       val = intel_uncore_read(uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
+       val = intel_mchbar_read(display, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
        if (val & DG1_GEAR_TYPE)
                sp->dclk *= 2;
 
        if (sp->dclk == 0)
                return -EINVAL;
 
-       val = intel_uncore_read(uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
+       val = intel_mchbar_read(display, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
        sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
        sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
 
-       val = intel_uncore_read(uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
+       val = intel_mchbar_read(display, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
        sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
        sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
index d655ed163f130f08e4c44e98b225d98a7a95ef6f..2079c63e3649fe75c10ac1ac66c336c9ccf7cabf 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -14,9 +14,9 @@
 #include "intel_display_utils.h"
 #include "intel_display_regs.h"
 #include "intel_dram.h"
+#include "intel_mchbar.h"
 #include "intel_mchbar_regs.h"
 #include "intel_parent.h"
-#include "intel_uncore.h"
 #include "vlv_sideband.h"
 
 struct dram_dimm_info {
@@ -59,18 +59,15 @@ const char *intel_dram_type_str(enum intel_dram_type type)
 
 static enum intel_dram_type pnv_dram_type(struct intel_display *display)
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
-
-       return intel_uncore_read(uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ?
+       return intel_mchbar_read(display, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ?
                INTEL_DRAM_DDR3 : INTEL_DRAM_DDR2;
 }
 
 static unsigned int pnv_mem_freq(struct intel_display *display)
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u32 tmp;
 
-       tmp = intel_uncore_read(uncore, CLKCFG);
+       tmp = intel_mchbar_read(display, CLKCFG);
 
        switch (tmp & CLKCFG_MEM_MASK) {
        case CLKCFG_MEM_533:
@@ -86,10 +83,9 @@ static unsigned int pnv_mem_freq(struct intel_display *display)
 
 static unsigned int ilk_mem_freq(struct intel_display *display)
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u16 ddrpll;
 
-       ddrpll = intel_uncore_read16(uncore, DDRMPLL1);
+       ddrpll = intel_mchbar_read16(display, DDRMPLL1);
        switch (ddrpll & 0xff) {
        case 0xc:
                return 800000;
@@ -159,7 +155,6 @@ unsigned int intel_mem_freq(struct intel_display *display)
 
 static unsigned int i9xx_fsb_freq(struct intel_display *display)
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u32 fsb;
 
        /*
@@ -170,7 +165,7 @@ static unsigned int i9xx_fsb_freq(struct intel_display *display)
         * don't know which registers have that information,
         * and all the relevant docs have gone to bit heaven :(
         */
-       fsb = intel_uncore_read(uncore, CLKCFG) & CLKCFG_FSB_MASK;
+       fsb = intel_mchbar_read(display, CLKCFG) & CLKCFG_FSB_MASK;
 
        if (display->platform.pineview || display->platform.mobile) {
                switch (fsb) {
@@ -215,10 +210,9 @@ static unsigned int i9xx_fsb_freq(struct intel_display *display)
 
 static unsigned int ilk_fsb_freq(struct intel_display *display)
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u16 fsb;
 
-       fsb = intel_uncore_read16(uncore, CSIPLL0) & 0x3ff;
+       fsb = intel_mchbar_read16(display, CSIPLL0) & 0x3ff;
 
        switch (fsb) {
        case 0x00c:
@@ -485,7 +479,6 @@ intel_is_dram_symmetric(const struct dram_channel_info *ch0,
 static int
 skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram_info)
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        struct dram_channel_info ch0 = {}, ch1 = {};
        u32 val;
        int ret;
@@ -493,12 +486,12 @@ skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram
        /* Assume 16Gb+ DIMMs are present until proven otherwise */
        dram_info->has_16gb_dimms = true;
 
-       val = intel_uncore_read(uncore, SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+       val = intel_mchbar_read(display, SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
        ret = skl_dram_get_channel_info(display, &ch0, 0, val);
        if (ret == 0)
                dram_info->num_channels++;
 
-       val = intel_uncore_read(uncore, SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
+       val = intel_mchbar_read(display, SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
        ret = skl_dram_get_channel_info(display, &ch1, 1, val);
        if (ret == 0)
                dram_info->num_channels++;
@@ -529,10 +522,9 @@ skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram
 static enum intel_dram_type
 skl_get_dram_type(struct intel_display *display)
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u32 val;
 
-       val = intel_uncore_read(uncore, SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
+       val = intel_mchbar_read(display, SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 
        switch (val & SKL_DRAM_DDR_TYPE_MASK) {
        case SKL_DRAM_DDR_TYPE_DDR3:
@@ -643,7 +635,6 @@ static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
 
 static int bxt_get_dram_info(struct intel_display *display, struct dram_info *dram_info)
 {
-       struct intel_uncore *uncore = to_intel_uncore(display->drm);
        u32 val;
        u8 valid_ranks = 0;
        int i;
@@ -655,7 +646,7 @@ static int bxt_get_dram_info(struct intel_display *display, struct dram_info *dr
                struct dram_dimm_info dimm;
                enum intel_dram_type type;
 
-               val = intel_uncore_read(uncore, BXT_D_CR_DRP0_DUNIT(i));
+               val = intel_mchbar_read(display, BXT_D_CR_DRP0_DUNIT(i));
                if (val == 0xFFFFFFFF)
                        continue;