perf/x86/intel: Add Airmont NP

The Intel / MaxLinear Airmont NP (aka Lightning Mountain) supports the
same architectual and non-architecural events as Airmont.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20251124074846.9653-3-ms@dev.tdt.de

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 0553c1160f15b43486fed0db1d5d8b8f0eeb4153..1840ca1918d1c17ac6de81765383cb249e1e1b95 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -7410,6 +7410,7 @@ __init int intel_pmu_init(void)
        case INTEL_ATOM_SILVERMONT_D:
        case INTEL_ATOM_SILVERMONT_MID:
        case INTEL_ATOM_AIRMONT:
+       case INTEL_ATOM_AIRMONT_NP:
        case INTEL_ATOM_SILVERMONT_MID2:
                memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
                        sizeof(hw_cache_event_ids));