CIDs set for MT6328, MT6331 and MT6332 are not appropriate.
Many Android downstream kernels define CID as below,
MT6328:
#define PMIC6328_E1_CID_CODE 0x2810
#define PMIC6328_E2_CID_CODE 0x2820
#define PMIC6328_E3_CID_CODE 0x2830
MT6331/MT6332:
#define PMIC6331_E1_CID_CODE 0x3110
#define PMIC6331_E2_CID_CODE 0x3120
#define PMIC6331_E3_CID_CODE 0x3130
#define PMIC6332_E1_CID_CODE 0x3210
#define PMIC6332_E2_CID_CODE 0x3220
#define PMIC6332_E3_CID_CODE 0x3230
The current configuration incorrectly uses the revision code as the CID.
Therefore, the driver cannot detect the same PMIC of different revisions.
(E1/E2 for MT6328, E1/E3 for MT6331/MT6332)
Based on these, the CID of MT6328, MT6331 and MT6332 should be corrected.
Additionally, the incorrect MT6331/MT6332 CID overlaps with the MT6320's
actual CID:
#define PMIC6320_E1_CID_CODE 0x1020
#define PMIC6320_E2_CID_CODE 0x2020
This causes a conflict in the switch-case statement of mt6397-irq.c,
this prevents adding support for MT6320.
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20260302140045.651727-1-akkun11.open@gmail.com
Signed-off-by: Lee Jones <lee@kernel.org>
static const struct chip_data mt6328_core = {
.cid_addr = MT6328_HWCID,
- .cid_shift = 0,
+ .cid_shift = 8,
.cells = mt6328_devs,
.cell_size = ARRAY_SIZE(mt6328_devs),
.irq_init = mt6397_irq_init,
static const struct chip_data mt6331_mt6332_core = {
.cid_addr = MT6331_HWCID,
- .cid_shift = 0,
+ .cid_shift = 8,
.cells = mt6331_mt6332_devs,
.cell_size = ARRAY_SIZE(mt6331_mt6332_devs),
.irq_init = mt6397_irq_init,
enum chip_id {
MT6323_CHIP_ID = 0x23,
- MT6328_CHIP_ID = 0x30,
- MT6331_CHIP_ID = 0x20,
- MT6332_CHIP_ID = 0x20,
+ MT6328_CHIP_ID = 0x28,
+ MT6331_CHIP_ID = 0x31,
+ MT6332_CHIP_ID = 0x32,
MT6357_CHIP_ID = 0x57,
MT6358_CHIP_ID = 0x58,
MT6359_CHIP_ID = 0x59,