Remove HAVE_AS_FMAF_HPC_VIS3 etc. on SPARC

The SPARC ISA extensions guarded by HAVE_AS_FMAF_HPC_VIS3 etc. have been
supported both in the Solaris as and GNU as for a long time.  The
original Solaris 11.4 as supports all of them, and gas support has been
added over time:

  HAVE_AS_FMAF_HPC_VIS3		-xarch=v9d		2.22
  HAVE_AS_SPARC4                -xarch=sparc4		2.23.1
  HAVE_AS_SPARC5_VIS4           -xarch=sparc5           2.25
  HAVE_AS_SPARC6                -xarch=sparc6           2.29

Solaris requires binutils 2.30 already on trunk, and 2.29 can be
expected on other SPARC targets, too, so this patch removes all code
that checks for their presence.

Bootstrapped without regressions on sparc-sun-solaris2.11 (as and gas),
sparcv9-sun-solaris2.11 (as), and sparc64-unknown-linux-gnu.

2026-02-14  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	gcc:
	* configure.ac <sparc*-*-*> (gcc_cv_as_sparc_fmaf): Remove.
	(gcc_cv_as_sparc_sparc4): Remove.
	(gcc_cv_as_sparc_sparc): Remove.
	(gcc_cv_as_sparc_sparc6): Remove.
	* configure: Regenerate.
	* config.in: Regenerate.

	* config/sparc/sparc.h (AS_NIAGARA3_FLAG) Remove.  Replace uses by
	definition.
	(AS_NIAGARA4_FLAG): Likewise.
	(AS_NIAGARA7_FLAG): Likewise.
	(AS_M8_FLAG): Likewise.
	* config/sparc/sol2.h [!HAVE_AS_SPARC4]: Remove.
	(AS_SPARC32_FLAG): Remove.
	(AS_SPARC64_FLAG): Remove.
	(AS_NIAGARA3_FLAG) Replace uses by definition.
	(AS_NIAGARA4_FLAG): Likewise.
	(AS_NIAGARA7_FLAG): Likewise.
	(AS_M8_FLAG): Likewise.
	* config/sparc/sparc.cc (sparc_option_override):
	[!HAVE_AS_FMAF_HPC_VIS3]: Remove.
	[!HAVE_AS_SPARC4]: Likewise.
	[!HAVE_AS_SPARC5_VIS4]: Likewise.
	[!HAVE_AS_SPARC6]: Likewise.

diff --git a/gcc/config.in b/gcc/config.in
index 1ff03986a158bee9f894617333bd36e80df0f1c9..faf382875dcd05e45a6bf04fa4ed8294473af2d3 100644 (file)
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -477,12 +477,6 @@
 #endif
 
 
-/* Define if your assembler supports FMAF, HPC, and VIS 3.0 instructions. */
-#ifndef USED_FOR_TARGET
-#undef HAVE_AS_FMAF_HPC_VIS3
-#endif
-
-
 /* Define if your assembler supports the --gdwarf2 option. */
 #ifndef USED_FOR_TARGET
 #undef HAVE_AS_GDWARF2_DEBUG_FLAG
@@ -786,24 +780,6 @@
 #endif
 
 
-/* Define if your assembler supports SPARC4 instructions. */
-#ifndef USED_FOR_TARGET
-#undef HAVE_AS_SPARC4
-#endif
-
-
-/* Define if your assembler supports SPARC5 and VIS 4.0 instructions. */
-#ifndef USED_FOR_TARGET
-#undef HAVE_AS_SPARC5_VIS4
-#endif
-
-
-/* Define if your assembler supports SPARC6 instructions. */
-#ifndef USED_FOR_TARGET
-#undef HAVE_AS_SPARC6
-#endif
-
-
 /* Define if your assembler supports call36 relocation. */
 #ifndef USED_FOR_TARGET
 #undef HAVE_AS_SUPPORT_CALL36

diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h
index fde5e388fbebb0625bd5870554f4246f62cf0518..d964c3ea727bb7a4d476c98babcbd16edfab2a2f 100644 (file)
--- a/gcc/config/sparc/sol2.h
+++ b/gcc/config/sparc/sol2.h
@@ -45,13 +45,8 @@ along with GCC; see the file COPYING3.  If not see
 
 /* Supposedly the same as vanilla sparc svr4, except for the stuff below: */
 
-/* If the assembler supports -xarch=sparc4, we switch to the explicit
-   word size selection mechanism available both in GNU as and Sun as,
-   for the Niagara4 and above configurations.  */
-#ifdef HAVE_AS_SPARC4
-
-#define AS_SPARC32_FLAG ""
-#define AS_SPARC64_FLAG ""
+/* We switch to the explicit word size selection mechanism available both in
+   GNU as and Sun as, for the Niagara4 and above configurations.  */
 
 #if !HAVE_GNU_AS
 #undef ASM_ARCH32_SPEC
@@ -64,37 +59,10 @@ along with GCC; see the file COPYING3.  If not see
 #undef ASM_SPEC
 #define ASM_SPEC ASM_SPEC_BASE " %(asm_arch)" ASM_PIC_SPEC
 
-#else /* HAVE_AS_SPARC4 */
-
-#define AS_SPARC32_FLAG "-xarch=v8plus"
-#define AS_SPARC64_FLAG "-xarch=v9"
-
-#undef AS_NIAGARA4_FLAG
-#define AS_NIAGARA4_FLAG AS_NIAGARA3_FLAG
-
-#undef ASM_ARCH32_SPEC
-#define ASM_ARCH32_SPEC ""
-
-#undef ASM_ARCH64_SPEC
-#define ASM_ARCH64_SPEC ""
-
-#undef ASM_ARCH_DEFAULT_SPEC
-#define ASM_ARCH_DEFAULT_SPEC ""
-
-#undef ASM_ARCH_SPEC
-#define ASM_ARCH_SPEC ""
-
-/* Both Sun as and GNU as understand -K PIC.  */
-#undef ASM_SPEC
-#define ASM_SPEC ASM_SPEC_BASE ASM_PIC_SPEC
-
-#endif /* HAVE_AS_SPARC4 */
-
-
 #undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAULT_SPEC ""
+#define ASM_CPU32_DEFAULT_SPEC ""
 #undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9"
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9"
 
 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
 #undef CPP_CPU64_DEFAULT_SPEC
@@ -143,36 +111,36 @@ along with GCC; see the file COPYING3.  If not see
 #undef CPP_CPU64_DEFAULT_SPEC
 #define CPP_CPU64_DEFAULT_SPEC ""
 #undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus" AS_NIAGARA3_FLAG
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusd"
 #undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9" AS_NIAGARA3_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9d"
 #endif
 
 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4
 #undef CPP_CPU64_DEFAULT_SPEC
 #define CPP_CPU64_DEFAULT_SPEC ""
 #undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAULT_SPEC AS_SPARC32_FLAG AS_NIAGARA4_FLAG
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=sparc4"
 #undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA4_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=sparc4"
 #endif
 
 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7
 #undef CPP_CPU64_DEFAULT_SPEC
 #define CPP_CPU64_DEFAULT_SPEC ""
 #undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAULT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=sparc5"
 #undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA7_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=sparc5"
 #endif
 
 #if TARGET_CPU_DEFAULT == TARGET_CPU_m8
 #undef CPP_CPU64_DEFAULT_SPEC
 #define CPP_CPU64_DEFAULT_SPEC ""
 #undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAULT_SPEC AS_SPARC32_FLAG AS_M8_FLAG
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=sparc6"
 #undef ASM_CPU64_DEFAULT_SPEC
-#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_M8_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=sparc6"
 #endif
 
 #undef CPP_CPU_SPEC
@@ -288,10 +256,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 %{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC("-xarch=v9b") "} \
 %{mcpu=niagara:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC("-xarch=v9b") "} \
 %{mcpu=niagara2:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC("-xarch=v9b") "} \
-%{mcpu=niagara3:" DEF_ARCH32_SPEC("-xarch=v8plus" AS_NIAGARA3_FLAG) DEF_ARCH64_SPEC("-xarch=v9" AS_NIAGARA3_FLAG) "} \
-%{mcpu=niagara4:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_NIAGARA4_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_NIAGARA4_FLAG) "} \
-%{mcpu=niagara7:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_NIAGARA7_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_NIAGARA7_FLAG) "} \
-%{mcpu=m8:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_M8_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_M8_FLAG) "} \
+%{mcpu=niagara3:" DEF_ARCH32_SPEC("-xarch=v8plusd") DEF_ARCH64_SPEC("-xarch=v9d") "} \
+%{mcpu=niagara4:" DEF_ARCH32_SPEC("-xarch=sparc4") DEF_ARCH64_SPEC("-xarch=sparc4") "} \
+%{mcpu=niagara7:" DEF_ARCH32_SPEC("-xarch=sparc5") DEF_ARCH64_SPEC("-xarch=sparc5") "} \
+%{mcpu=m8:" DEF_ARCH32_SPEC("-xarch=sparc6") DEF_ARCH64_SPEC("-xarch=sparc6") "} \
 %{!mcpu=m8:%{!mcpu=niagara7:%{!mcpu=niagara4:%{!mcpu=niagara3:%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC("-xarch=v9") "}}}}}}}}}} \
 %{!mcpu*:%(asm_cpu_default)} \
 "

diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc
index 18e76afb57de3dd2cec53225d4c2abde68e0381d..47559dbe2cd135607b51ecf13e874d5e0ffabfff 100644 (file)
--- a/gcc/config/sparc/sparc.cc
+++ b/gcc/config/sparc/sparc.cc
@@ -1891,18 +1891,6 @@ sparc_option_override (void)
 
   target_flags &= ~cpu->disable;
   target_flags |= (cpu->enable
-#ifndef HAVE_AS_FMAF_HPC_VIS3
-                  & ~(MASK_FMAF | MASK_VIS3)
-#endif
-#ifndef HAVE_AS_SPARC4
-                  & ~MASK_CBCOND
-#endif
-#ifndef HAVE_AS_SPARC5_VIS4
-                  & ~(MASK_VIS4 | MASK_SUBXC)
-#endif
-#ifndef HAVE_AS_SPARC6
-                  & ~(MASK_VIS4B)
-#endif
 #ifndef HAVE_AS_LEON
                   & ~(MASK_LEON | MASK_LEON3)
 #endif

diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 87a3f9da89bff059ad0c7eec41a94f70e6302db4..fd406f36c8a7dc75e0dabf3904c899b30e84ccd8 100644 (file)
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -174,19 +174,19 @@ along with GCC; see the file COPYING3.  If not see
 #endif
 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3
 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
-#define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-Av9d"
 #endif
 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4
 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
-#define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=sparc4"
 #endif
 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7
 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
-#define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=sparc5"
 #endif
 #if TARGET_CPU_DEFAULT == TARGET_CPU_m8
 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
-#define ASM_CPU64_DEFAULT_SPEC AS_M8_FLAG
+#define ASM_CPU64_DEFAULT_SPEC "-xarch=sparc6"
 #endif
 
 #else
@@ -344,10 +344,10 @@ along with GCC; see the file COPYING3.  If not see
 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
 %{mcpu=niagara:%{!mv8plus:-Av9b}} \
 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \
-%{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \
-%{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \
-%{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \
-%{mcpu=m8:%{!mv8plus:" AS_M8_FLAG "}} \
+%{mcpu=niagara3:%{!mv8plus:-Av9d}} \
+%{mcpu=niagara4:%{!mv8plus:-xarch=sparc4}} \
+%{mcpu=niagara7:%{!mv8plus:-xarch=sparc5}} \
+%{mcpu=m8:%{!mv8plus:-xarch=sparc6}} \
 %{!mcpu*:%(asm_cpu_default)} \
 "
 
@@ -1624,30 +1624,6 @@ extern int sparc_indent_opcode;
    activated in separate configuration files.  */
 #define TARGET_TLS HAVE_AS_TLS
 
-#ifdef HAVE_AS_FMAF_HPC_VIS3
-#define AS_NIAGARA3_FLAG "d"
-#else
-#define AS_NIAGARA3_FLAG "b"
-#endif
-
-#ifdef HAVE_AS_SPARC4
-#define AS_NIAGARA4_FLAG "-xarch=sparc4"
-#else
-#define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG
-#endif
-
-#ifdef HAVE_AS_SPARC5_VIS4
-#define AS_NIAGARA7_FLAG "-xarch=sparc5"
-#else
-#define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG
-#endif
-
-#ifdef HAVE_AS_SPARC6
-#define AS_M8_FLAG "-xarch=sparc6"
-#else
-#define AS_M8_FLAG AS_NIAGARA7_FLAG
-#endif
-
 #ifdef HAVE_AS_LEON
 #define AS_LEON_FLAG "-Aleon"
 #define AS_LEONV7_FLAG "-Aleon"

diff --git a/gcc/configure b/gcc/configure
index f716bffaf839c7205720a75aeb7d484b951b9df7..7dc17f4cc205802473c1b9c4e4aebf59b2e2ab37 100755 (executable)
--- a/gcc/configure
+++ b/gcc/configure
@@ -29264,162 +29264,6 @@ if test $gcc_cv_as_sparc_offsetable_lo10 = yes; then
 
 $as_echo "#define HAVE_AS_OFFSETABLE_LO10 1" >>confdefs.h
 
-fi
-
-
-    { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for FMAF, HPC, and VIS 3.0 instructions" >&5
-$as_echo_n "checking assembler for FMAF, HPC, and VIS 3.0 instructions... " >&6; }
-if ${gcc_cv_as_sparc_fmaf+:} false; then :
-  $as_echo_n "(cached) " >&6
-else
-  gcc_cv_as_sparc_fmaf=no
-  if test x"$gcc_cv_as" != x; then
-    $as_echo '.text
-       .register %g2, #scratch
-       .register %g3, #scratch
-       .align 4
-       fmaddd %f0, %f2, %f4, %f6
-       addxccc %g1, %g2, %g3
-       fsrl32 %f2, %f4, %f8
-       fnaddd %f10, %f12, %f14' > conftest.s
-    if { ac_try='$gcc_cv_as $gcc_cv_as_flags -xarch=v9d -o conftest.o conftest.s >&5'
-  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
-  test $ac_status = 0; }; }
-    then
-       gcc_cv_as_sparc_fmaf=yes
-    else
-      echo "configure: failed program was" >&5
-      cat conftest.s >&5
-    fi
-    rm -f conftest.o conftest.s
-  fi
-fi
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_fmaf" >&5
-$as_echo "$gcc_cv_as_sparc_fmaf" >&6; }
-if test $gcc_cv_as_sparc_fmaf = yes; then
-
-$as_echo "#define HAVE_AS_FMAF_HPC_VIS3 1" >>confdefs.h
-
-fi
-
-
-    { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for SPARC4 instructions" >&5
-$as_echo_n "checking assembler for SPARC4 instructions... " >&6; }
-if ${gcc_cv_as_sparc_sparc4+:} false; then :
-  $as_echo_n "(cached) " >&6
-else
-  gcc_cv_as_sparc_sparc4=no
-  if test x"$gcc_cv_as" != x; then
-    $as_echo '.text
-       .register %g2, #scratch
-       .register %g3, #scratch
-       .align 4
-       cxbe %g2, %g3, 1f
-1:     cwbneg %g2, %g3, 1f
-1:     sha1
-       md5
-       aes_kexpand0 %f4, %f6, %f8
-       des_round %f38, %f40, %f42, %f44
-       camellia_f %f54, %f56, %f58, %f60
-       kasumi_fi_xor %f46, %f48, %f50, %f52' > conftest.s
-    if { ac_try='$gcc_cv_as $gcc_cv_as_flags -xarch=sparc4 -o conftest.o conftest.s >&5'
-  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
-  test $ac_status = 0; }; }
-    then
-       gcc_cv_as_sparc_sparc4=yes
-    else
-      echo "configure: failed program was" >&5
-      cat conftest.s >&5
-    fi
-    rm -f conftest.o conftest.s
-  fi
-fi
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_sparc4" >&5
-$as_echo "$gcc_cv_as_sparc_sparc4" >&6; }
-if test $gcc_cv_as_sparc_sparc4 = yes; then
-
-$as_echo "#define HAVE_AS_SPARC4 1" >>confdefs.h
-
-fi
-
-
-    { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for SPARC5 and VIS 4.0 instructions" >&5
-$as_echo_n "checking assembler for SPARC5 and VIS 4.0 instructions... " >&6; }
-if ${gcc_cv_as_sparc_sparc5+:} false; then :
-  $as_echo_n "(cached) " >&6
-else
-  gcc_cv_as_sparc_sparc5=no
-  if test x"$gcc_cv_as" != x; then
-    $as_echo '.text
-       .register %g2, #scratch
-       .register %g3, #scratch
-       .align 4
-       subxc %g1, %g2, %g3
-       fpadd8 %f0, %f2, %f4' > conftest.s
-    if { ac_try='$gcc_cv_as $gcc_cv_as_flags -xarch=sparc5 -o conftest.o conftest.s >&5'
-  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
-  test $ac_status = 0; }; }
-    then
-       gcc_cv_as_sparc_sparc5=yes
-    else
-      echo "configure: failed program was" >&5
-      cat conftest.s >&5
-    fi
-    rm -f conftest.o conftest.s
-  fi
-fi
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_sparc5" >&5
-$as_echo "$gcc_cv_as_sparc_sparc5" >&6; }
-if test $gcc_cv_as_sparc_sparc5 = yes; then
-
-$as_echo "#define HAVE_AS_SPARC5_VIS4 1" >>confdefs.h
-
-fi
-
-
-    { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for SPARC6 instructions" >&5
-$as_echo_n "checking assembler for SPARC6 instructions... " >&6; }
-if ${gcc_cv_as_sparc_sparc6+:} false; then :
-  $as_echo_n "(cached) " >&6
-else
-  gcc_cv_as_sparc_sparc6=no
-  if test x"$gcc_cv_as" != x; then
-    $as_echo '.text
-       .register %g2, #scratch
-       .register %g3, #scratch
-       .align 4
-       rd %entropy, %g1
-       fpsll64x %f0, %f2, %f4' > conftest.s
-    if { ac_try='$gcc_cv_as $gcc_cv_as_flags -xarch=sparc6 -o conftest.o conftest.s >&5'
-  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
-  test $ac_status = 0; }; }
-    then
-       gcc_cv_as_sparc_sparc6=yes
-    else
-      echo "configure: failed program was" >&5
-      cat conftest.s >&5
-    fi
-    rm -f conftest.o conftest.s
-  fi
-fi
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_sparc6" >&5
-$as_echo "$gcc_cv_as_sparc_sparc6" >&6; }
-if test $gcc_cv_as_sparc_sparc6 = yes; then
-
-$as_echo "#define HAVE_AS_SPARC6 1" >>confdefs.h
-
 fi
 
 

diff --git a/gcc/configure.ac b/gcc/configure.ac
index 2ebecf7c91f03f172edb62b1c52dd59c4caffc39..a10d714a3c9cfbf4c18db708261c9a48f35c01c4 100644 (file)
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -4744,62 +4744,6 @@ EOF
        [AC_DEFINE(HAVE_AS_OFFSETABLE_LO10, 1,
                 [Define if your assembler supports offsetable %lo().])])
 
-    gcc_GAS_CHECK_FEATURE([FMAF, HPC, and VIS 3.0 instructions],
-      gcc_cv_as_sparc_fmaf,
-      [-xarch=v9d],
-      [.text
-       .register %g2, #scratch
-       .register %g3, #scratch
-       .align 4
-       fmaddd %f0, %f2, %f4, %f6
-       addxccc %g1, %g2, %g3
-       fsrl32 %f2, %f4, %f8
-       fnaddd %f10, %f12, %f14],,
-      [AC_DEFINE(HAVE_AS_FMAF_HPC_VIS3, 1,
-                [Define if your assembler supports FMAF, HPC, and VIS 3.0 instructions.])])
-
-    gcc_GAS_CHECK_FEATURE([SPARC4 instructions],
-      gcc_cv_as_sparc_sparc4,
-      [-xarch=sparc4],
-      [.text
-       .register %g2, #scratch
-       .register %g3, #scratch
-       .align 4
-       cxbe %g2, %g3, 1f
-1:     cwbneg %g2, %g3, 1f
-1:     sha1
-       md5
-       aes_kexpand0 %f4, %f6, %f8
-       des_round %f38, %f40, %f42, %f44
-       camellia_f %f54, %f56, %f58, %f60
-       kasumi_fi_xor %f46, %f48, %f50, %f52],,
-      [AC_DEFINE(HAVE_AS_SPARC4, 1,
-                [Define if your assembler supports SPARC4 instructions.])])
-
-    gcc_GAS_CHECK_FEATURE([SPARC5 and VIS 4.0 instructions],
-      gcc_cv_as_sparc_sparc5,
-      [-xarch=sparc5],
-      [.text
-       .register %g2, #scratch
-       .register %g3, #scratch
-       .align 4
-       subxc %g1, %g2, %g3
-       fpadd8 %f0, %f2, %f4],,
-      [AC_DEFINE(HAVE_AS_SPARC5_VIS4, 1,
-                [Define if your assembler supports SPARC5 and VIS 4.0 instructions.])])
-
-    gcc_GAS_CHECK_FEATURE([SPARC6 instructions],
-      gcc_cv_as_sparc_sparc6,
-      [-xarch=sparc6],
-      [.text
-       .register %g2, #scratch
-       .register %g3, #scratch
-       .align 4
-       rd %entropy, %g1
-       fpsll64x %f0, %f2, %f4],,
-      [AC_DEFINE(HAVE_AS_SPARC6, 1,
-                [Define if your assembler supports SPARC6 instructions.])])
-
     gcc_GAS_CHECK_FEATURE([LEON instructions],
       gcc_cv_as_sparc_leon,
       [-Aleon],