reset: spacemit: k3: Decouple composite reset lines

Instead of grouping several different reset lines into one composite
reset, decouple them to individual ones which make it more aligned
with underlying hardware. And for DWC USB driver, it will match well
with the number of the reset property in the DT bindings.

The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.
Also three reset lines each for UCIE and RCPU block.

As an agreement with maintainer, the reset IDs has been rearranged as
contiguous number but keep most part unchanged to avoid break patches
which already sent to mailing list. The changes of DT binding header file
and reset driver are merged together as one single commit to avoid
git-bisect breakage.

Fixes: 938ce3b16582 ("reset: spacemit: Add SpacemiT K3 reset driver")
Fixes: 216e0a5e98e5 ("dt-bindings: soc: spacemit: Add K3 reset support and IDs")
Signed-off-by: Yixun Lan <dlan@kernel.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c
index e9e32e4c1ba562dd72ccfdd5a529f7f1e20222c5..9841f5e057b2a0ce65513d2d2db4c1cbdbf39f6d 100644 (file)
--- a/drivers/reset/spacemit/reset-spacemit-k3.c
+++ b/drivers/reset/spacemit/reset-spacemit-k3.c
@@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
        [RESET_APMU_SDH0]       = RESET_DATA(APMU_SDH0_CLK_RES_CTRL,    0, BIT(1)),
        [RESET_APMU_SDH1]       = RESET_DATA(APMU_SDH1_CLK_RES_CTRL,    0, BIT(1)),
        [RESET_APMU_SDH2]       = RESET_DATA(APMU_SDH2_CLK_RES_CTRL,    0, BIT(1)),
-       [RESET_APMU_USB2]       = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0,
-                               BIT(1)|BIT(2)|BIT(3)),
-       [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0,
-                               BIT(5)|BIT(6)|BIT(7)),
-       [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0,
-                               BIT(9)|BIT(10)|BIT(11)),
-       [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0,
-                               BIT(13)|BIT(14)|BIT(15)),
-       [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0,
-                               BIT(17)|BIT(18)|BIT(19)),
+       [RESET_APMU_USB2_AHB]   = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(1)),
+       [RESET_APMU_USB2_VCC]   = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(2)),
+       [RESET_APMU_USB2_PHY]   = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(3)),
+       [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(5)),
+       [RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(6)),
+       [RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(7)),
+       [RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(9)),
+       [RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(10)),
+       [RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(11)),
+       [RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(13)),
+       [RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(14)),
+       [RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(15)),
+       [RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(17)),
+       [RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(18)),
+       [RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL,     0, BIT(19)),
        [RESET_APMU_QSPI]       = RESET_DATA(APMU_QSPI_CLK_RES_CTRL,    0, BIT(1)),
        [RESET_APMU_QSPI_BUS]   = RESET_DATA(APMU_QSPI_CLK_RES_CTRL,    0, BIT(0)),
        [RESET_APMU_DMA]        = RESET_DATA(APMU_DMA_CLK_RES_CTRL,     0, BIT(0)),
@@ -151,10 +156,12 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
        [RESET_APMU_CPU7_SW]    = RESET_DATA(APMU_PMU_CC2_AP,           BIT(26), 0),
        [RESET_APMU_C1_MPSUB_SW]        = RESET_DATA(APMU_PMU_CC2_AP,   BIT(28), 0),
        [RESET_APMU_MPSUB_DBG]  = RESET_DATA(APMU_PMU_CC2_AP,           BIT(29), 0),
-       [RESET_APMU_UCIE]       = RESET_DATA(APMU_UCIE_CTRL,
-                               BIT(1) | BIT(2) | BIT(3), 0),
-       [RESET_APMU_RCPU]       = RESET_DATA(APMU_RCPU_CLK_RES_CTRL,    0,
-                               BIT(3) | BIT(2) | BIT(0)),
+       [RESET_APMU_UCIE_IP]    = RESET_DATA(APMU_UCIE_CTRL,            BIT(1),  0),
+       [RESET_APMU_UCIE_HOT]   = RESET_DATA(APMU_UCIE_CTRL,            BIT(2),  0),
+       [RESET_APMU_UCIE_MON]   = RESET_DATA(APMU_UCIE_CTRL,            BIT(3),  0),
+       [RESET_APMU_RCPU_AUDIO_SYS]     = RESET_DATA(APMU_RCPU_CLK_RES_CTRL,    0, BIT(0)),
+       [RESET_APMU_RCPU_MCU_CORE]      = RESET_DATA(APMU_RCPU_CLK_RES_CTRL,    0, BIT(2)),
+       [RESET_APMU_RCPU_AUDIO_APMU]    = RESET_DATA(APMU_RCPU_CLK_RES_CTRL,    0, BIT(3)),
        [RESET_APMU_DSI4LN2_ESCCLK]     = RESET_DATA(APMU_LCD_CLK_RES_CTRL3,    0, BIT(3)),
        [RESET_APMU_DSI4LN2_LCD_SW]     = RESET_DATA(APMU_LCD_CLK_RES_CTRL3,    0, BIT(4)),
        [RESET_APMU_DSI4LN2_LCD_MCLK]   = RESET_DATA(APMU_LCD_CLK_RES_CTRL4,    0, BIT(9)),
@@ -164,16 +171,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
        [RESET_APMU_UFS_ACLK]   = RESET_DATA(APMU_UFS_CLK_RES_CTRL,     0, BIT(0)),
        [RESET_APMU_EDP0]       = RESET_DATA(APMU_LCD_EDP_CTRL,         0, BIT(0)),
        [RESET_APMU_EDP1]       = RESET_DATA(APMU_LCD_EDP_CTRL,         0, BIT(16)),
-       [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,  0,
-                               BIT(5) | BIT(4) | BIT(3)),
-       [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,  0,
-                               BIT(5) | BIT(4) | BIT(3)),
-       [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,  0,
-                               BIT(5) | BIT(4) | BIT(3)),
-       [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,  0,
-                               BIT(5) | BIT(4) | BIT(3)),
-       [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,  0,
-                               BIT(5) | BIT(4) | BIT(3)),
+       [RESET_APMU_PCIE_A_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,  0, BIT(3)),
+       [RESET_APMU_PCIE_A_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,  0, BIT(4)),
+       [RESET_APMU_PCIE_A_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,  0, BIT(5)),
+       [RESET_APMU_PCIE_B_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,  0, BIT(3)),
+       [RESET_APMU_PCIE_B_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,  0, BIT(4)),
+       [RESET_APMU_PCIE_B_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,  0, BIT(5)),
+       [RESET_APMU_PCIE_C_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,  0, BIT(3)),
+       [RESET_APMU_PCIE_C_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,  0, BIT(4)),
+       [RESET_APMU_PCIE_C_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,  0, BIT(5)),
+       [RESET_APMU_PCIE_D_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,  0, BIT(3)),
+       [RESET_APMU_PCIE_D_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,  0, BIT(4)),
+       [RESET_APMU_PCIE_D_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,  0, BIT(5)),
+       [RESET_APMU_PCIE_E_DBI]         = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,  0, BIT(3)),
+       [RESET_APMU_PCIE_E_SLAVE]       = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,  0, BIT(4)),
+       [RESET_APMU_PCIE_E_MASTER]      = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,  0, BIT(5)),
        [RESET_APMU_EMAC0]      = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL,   0, BIT(1)),
        [RESET_APMU_EMAC1]      = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL,   0, BIT(1)),
        [RESET_APMU_EMAC2]      = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL,   0, BIT(1)),

diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
index 79ac1c22b7b5447af1596edcb67a5dfa981e9ee7..dc1ef009ba797214b48e25037f283a382ee35aef 100644 (file)
--- a/include/dt-bindings/reset/spacemit,k3-resets.h
+++ b/include/dt-bindings/reset/spacemit,k3-resets.h
@@ -97,11 +97,11 @@
 #define RESET_APMU_SDH0          13
 #define RESET_APMU_SDH1          14
 #define RESET_APMU_SDH2          15
-#define RESET_APMU_USB2          16
-#define RESET_APMU_USB3_PORTA    17
-#define RESET_APMU_USB3_PORTB    18
-#define RESET_APMU_USB3_PORTC    19
-#define RESET_APMU_USB3_PORTD    20
+#define RESET_APMU_USB2_AHB      16
+#define RESET_APMU_USB2_VCC      17
+#define RESET_APMU_USB2_PHY      18
+#define RESET_APMU_USB3_A_AHB    19
+#define RESET_APMU_USB3_A_VCC    20
 #define RESET_APMU_QSPI          21
 #define RESET_APMU_QSPI_BUS      22
 #define RESET_APMU_DMA           23
@@ -132,8 +132,8 @@
 #define RESET_APMU_CPU7_SW       48
 #define RESET_APMU_C1_MPSUB_SW   49
 #define RESET_APMU_MPSUB_DBG     50
-#define RESET_APMU_UCIE          51
-#define RESET_APMU_RCPU          52
+#define RESET_APMU_USB3_A_PHY    51    /* USB3 A */
+#define RESET_APMU_USB3_B_AHB    52
 #define RESET_APMU_DSI4LN2_ESCCLK     53
 #define RESET_APMU_DSI4LN2_LCD_SW     54
 #define RESET_APMU_DSI4LN2_LCD_MCLK   55
@@ -143,16 +143,40 @@
 #define RESET_APMU_UFS_ACLK      59
 #define RESET_APMU_EDP0          60
 #define RESET_APMU_EDP1          61
-#define RESET_APMU_PCIE_PORTA    62
-#define RESET_APMU_PCIE_PORTB    63
-#define RESET_APMU_PCIE_PORTC    64
-#define RESET_APMU_PCIE_PORTD    65
-#define RESET_APMU_PCIE_PORTE    66
+#define RESET_APMU_USB3_B_VCC    62    /* USB3 B */
+#define RESET_APMU_USB3_B_PHY    63
+#define RESET_APMU_USB3_C_AHB    64
+#define RESET_APMU_USB3_C_VCC    65
+#define RESET_APMU_USB3_C_PHY    66
 #define RESET_APMU_EMAC0         67
 #define RESET_APMU_EMAC1         68
 #define RESET_APMU_EMAC2         69
 #define RESET_APMU_ESPI_MCLK     70
 #define RESET_APMU_ESPI_SCLK     71
+#define RESET_APMU_USB3_D_AHB    72    /* USB3 D */
+#define RESET_APMU_USB3_D_VCC    73
+#define RESET_APMU_USB3_D_PHY    74
+#define RESET_APMU_UCIE_IP       75
+#define RESET_APMU_UCIE_HOT      76
+#define RESET_APMU_UCIE_MON      77
+#define RESET_APMU_RCPU_AUDIO_SYS     78
+#define RESET_APMU_RCPU_MCU_CORE      79
+#define RESET_APMU_RCPU_AUDIO_APMU    80
+#define RESET_APMU_PCIE_A_DBI    81
+#define RESET_APMU_PCIE_A_SLAVE  82
+#define RESET_APMU_PCIE_A_MASTER 83
+#define RESET_APMU_PCIE_B_DBI    84
+#define RESET_APMU_PCIE_B_SLAVE  85
+#define RESET_APMU_PCIE_B_MASTER 86
+#define RESET_APMU_PCIE_C_DBI    87
+#define RESET_APMU_PCIE_C_SLAVE  88
+#define RESET_APMU_PCIE_C_MASTER 89
+#define RESET_APMU_PCIE_D_DBI    90
+#define RESET_APMU_PCIE_D_SLAVE  91
+#define RESET_APMU_PCIE_D_MASTER 92
+#define RESET_APMU_PCIE_E_DBI    93
+#define RESET_APMU_PCIE_E_SLAVE  94
+#define RESET_APMU_PCIE_E_MASTER 95
 
 /* DCIU resets*/
 #define RESET_DCIU_HDMA          0