dmaengine: qcom: gpi: Add GPI immediate DMA support for SPI protocol

The DMA TRE(Transfer ring element) buffer contains the DMA
buffer address. Accessing data from this address can cause
significant delays in SPI transfers, which can be mitigated to
some extent by utilizing immediate DMA support.

QCOM GPI DMA hardware supports an immediate DMA feature for data
up to 8 bytes, storing the data directly in the DMA TRE buffer
instead of the DMA buffer address. This enhancement enables faster
SPI data transfers.

This optimization reduces the average transfer time from 25 us to
16 us for a single SPI transfer of 8 bytes length, with a clock
frequency of 50 MHz.

Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241209075033.16860-1-quic_jseerapu@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c
index 52a7c8f2498f61a5dfe0a62bbca1b66bb3119a40..b1f0001cc99c7066b6d08f53d9381d4fd22588ca 100644 (file)
--- a/drivers/dma/qcom/gpi.c
+++ b/drivers/dma/qcom/gpi.c
@@ -18,6 +18,7 @@
 #include "../virt-dma.h"
 
 #define TRE_TYPE_DMA           0x10
+#define TRE_TYPE_IMMEDIATE_DMA 0x11
 #define TRE_TYPE_GO            0x20
 #define TRE_TYPE_CONFIG0       0x22
 
@@ -64,6 +65,7 @@
 
 /* DMA TRE */
 #define TRE_DMA_LEN            GENMASK(23, 0)
+#define TRE_DMA_IMMEDIATE_LEN  GENMASK(3, 0)
 
 /* Register offsets from gpi-top */
 #define GPII_n_CH_k_CNTXT_0_OFFS(n, k) (0x20000 + (0x4000 * (n)) + (0x80 * (k)))
@@ -1711,6 +1713,7 @@ static int gpi_create_spi_tre(struct gchan *chan, struct gpi_desc *desc,
        dma_addr_t address;
        struct gpi_tre *tre;
        unsigned int i;
+       int len;
 
        /* first create config tre if applicable */
        if (direction == DMA_MEM_TO_DEV && spi->set_config) {
@@ -1763,14 +1766,30 @@ static int gpi_create_spi_tre(struct gchan *chan, struct gpi_desc *desc,
        tre_idx++;
 
        address = sg_dma_address(sgl);
-       tre->dword[0] = lower_32_bits(address);
-       tre->dword[1] = upper_32_bits(address);
+       len = sg_dma_len(sgl);
 
-       tre->dword[2] = u32_encode_bits(sg_dma_len(sgl), TRE_DMA_LEN);
+       /* Support Immediate dma for write transfers for data length up to 8 bytes */
+       if (direction == DMA_MEM_TO_DEV && len <= 2 * sizeof(tre->dword[0])) {
+               /*
+                * For Immediate dma, data length may not always be length of 8 bytes,
+                * it can be length less than 8, hence initialize both dword's with 0
+                */
+               tre->dword[0] = 0;
+               tre->dword[1] = 0;
+               memcpy(&tre->dword[0], sg_virt(sgl), len);
 
-       tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE);
-       if (direction == DMA_MEM_TO_DEV)
-               tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT);
+               tre->dword[2] = u32_encode_bits(len, TRE_DMA_IMMEDIATE_LEN);
+               tre->dword[3] = u32_encode_bits(TRE_TYPE_IMMEDIATE_DMA, TRE_FLAGS_TYPE);
+       } else {
+               tre->dword[0] = lower_32_bits(address);
+               tre->dword[1] = upper_32_bits(address);
+
+               tre->dword[2] = u32_encode_bits(len, TRE_DMA_LEN);
+               tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE);
+       }
+
+       tre->dword[3] |= u32_encode_bits(direction == DMA_MEM_TO_DEV,
+                                        TRE_FLAGS_IEOT);
 
        for (i = 0; i < tre_idx; i++)
                dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0],