phy: renesas: rcar-gen3-usb2: Set timing registers only once

commit 86e70849f4b2b4597ac9f7c7931f2a363774be25 upstream.

phy-rcar-gen3-usb2 driver exports 4 PHYs. The timing registers are common
to all PHYs. There is no need to set them every time a PHY is initialized.
Set timing register only when the 1st PHY is initialized.

Fixes: f3b5a8d9b50d ("phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver")
Cc: stable@vger.kernel.org
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20250507125032.565017-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index 44bb76972955c4a5a49fbc799cbf039ba02198fa..aa578be2bcb6df3f446c582eba4c09b9405cd45a 100644 (file)
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -452,8 +452,11 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
        val = readl(usb2_base + USB2_INT_ENABLE);
        val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits;
        writel(val, usb2_base + USB2_INT_ENABLE);
-       writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
-       writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
+
+       if (!rcar_gen3_is_any_rphy_initialized(channel)) {
+               writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
+               writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
+       }
 
        /* Initialize otg part (only if we initialize a PHY with IRQs). */
        if (rphy->int_enable_bits)