Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c6cdcc3a1dbbd79419a9b626ae56a301c19ca6e4..33e4b506765e2afbc14aff0a4f2f061c61acfc09 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2023-04-16  Jeff Law  <jlaw@ventanamicro>
+
+       PR target/109508
+       * config/riscv/riscv.cc (riscv_expand_conditional_move): For
+       TARGET_SFB_ALU, force the true arm into a register.
+
 2023-04-15  John David Anglin  <danglin@gcc.gnu.org>
 
        PR target/104989

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ba4f30bf04867e029ee61dd462cf601cda631cbb..27b1d3f07db7ed48ca27c2a01dbb7178a8ddce5f 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230416
+20230417

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 443ba5f48f4c50fa275de9b4d931f6cf940d4b6c..2cda0bfd4e4bbea0634485070f5296d68d0f6eaf 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2023-04-16  Jeff Law  <jlaw@ventanamicro>
+
+       PR target/109508
+       * gcc.target/riscv/pr109508.c: New test.
+
+2023-04-16  Roger Sayle  <roger@nextmovesoftware.com>
+
+       PR target/54816
+       * gcc.target/avr/pr54816.c: New test case.
+
 2023-04-15  Jason Merrill  <jason@redhat.com>
 
        PR c++/109357